URL https://opencores.org/ocsvn/turbo8051/turbo8051/trunk

Subversion Repositories turbo8051

[/] [turbo8051/] [trunk/] [verif/] [tb/] [tb_top.v] - Diff between revs 73 and 76

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Rev 73	Rev 76
Line 39...	Line 39...
`//// from http://www.opencores.org/lgpl.shtml ////`	`//// from http://www.opencores.org/lgpl.shtml ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`


`timescale 1ns/1ps

`include "tb_defines.v"	`include "tb_defines.v"

`module tb_top;`	`module tb_top;`

Line 158...	Line 157...
`wire wb_xram_stb ; // data-ram strobe`	`wire wb_xram_stb ; // data-ram strobe`
`wire wb_xram_cyc ; // data-ram cycle`	`wire wb_xram_cyc ; // data-ram cycle`

`//----------------------------------------`	`//----------------------------------------`

`turbo8051 u_core (`	`digital_core u_core (`

`. reset_n (reset_n ),`	`. reset_n (reset_n ),`
`. fastsim_mode (1'b1 ),`	`. fastsim_mode (1'b1 ),`
`. mastermode (master_mode ),`	`. mastermode (master_mode ),`

Line 192...	Line 191...
`.phy_rx_clk (phy_rx_clk ),`	`.phy_rx_clk (phy_rx_clk ),`
`.phy_rx_dv (phy_rx_dv ),`	`.phy_rx_dv (phy_rx_dv ),`
`.phy_rxd (phy_rxd ),`	`.phy_rxd (phy_rxd ),`

`//MDIO interface`	`//MDIO interface`
`.MDC (MDC ),`	`//.MDC (MDC ),`
`.MDIO (MDIO ),`	`//.MDIO (MDIO ),`


`// UART Line Interface`	`// UART Line Interface`
`.si (si ),`	`.si (si ),`
`.so (so ),`	`.so (so ),`
Line 391...	Line 390...
`$fsdbDumpon;`	`$fsdbDumpon;`
`end`	`end`
`end`	`end`
`endif	`endif

	`initial begin //{`
	`$display ("--> Dumpping the design");`
	`$shm_open("simvision.shm");`
	`$shm_probe("AC");`
	`end //}`


`initial begin`	`initial begin`

`if ( $test$plusargs("INTERNAL_ROM") ) begin`	`if ( $test$plusargs("INTERNAL_ROM") ) begin`
`ea_in = 1;`	`ea_in = 1;`
`master_mode = 1;`	`master_mode = 1;`

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Subversion Repositories turbo8051

[/] [turbo8051/] [trunk/] [verif/] [tb/] [tb_top.v] - Diff between revs 73 and 76