URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [branches/] [restruc1/] [doc/] [tv80_docs.xml] - Diff between revs 29 and 35

Rev 29	Rev 35
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`tv80 Core Documentation`	`tv80 Core Documentation`

Line 98...	Line 98...

`When set, starts a countdown (in clocks) until assertion of`	`When set, starts a countdown (in clocks) until assertion of`
`the INT_N signal.`	`the INT_N signal.`



	`This register holds the checksum value of all data`
	`written to the accumulate register. The checksum is a simple`
	`twos-complement checksum, so it can be compared with a CPU-generated`
	`checksum.`
	`This register is readable and writeable. Writing the register sets`
	`the current checksum value.`


	`This write-only register adds the written value to the value`
	`contained in the Checksum Value register.`


	`This register increments every time it is read, so reading it`
	`repeatedly generates an incrementing sequence. It can be reset`
	`by writing it to a new starting value.`




`The minimum toolchain required to simulate the tv80 is the`	`The minimum toolchain required to simulate the tv80 is the`
`CVer Verilog simulator, and the`	`CVer Verilog simulator, and the`