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[/] [tv80/] [branches/] [restruc1/] [rtl/] [core/] [tv80_mcode.v] - Diff between revs 21 and 23

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Rev 21 Rev 23
Line 44... Line 44... 
  parameter             Flag_Z = 6;
 
  parameter             Flag_Z = 6;
 
  parameter             Flag_S = 7;
 
  parameter             Flag_S = 7;
 
 
 
 
 
  input [7:0]           IR;
 
  input [7:0]           IR;
 
  input [1:0]           ISet                     ;
 
  input [1:0]           ISet                     ;
 
  input [2:0]           MCycle                   ;
 
  input [6:0]           MCycle                   ;
 
  input [7:0]           F                        ;
 
  input [7:0]           F                        ;
 
  input                 NMICycle                ;
 
  input                 NMICycle                ;
 
  input                 IntCycle                ;
 
  input                 IntCycle                ;
 
  output [2:0]          MCycles                  ;
 
  output [2:0]          MCycles                  ;
 
  output [2:0]          TStates                  ;
 
  output [2:0]          TStates                  ;
Line 291... Line 291... 
 
 
 
 
              8'b00000110,8'b00001110,8'b00010110,8'b00011110,8'b00100110,8'b00101110,8'b00111110  :
 
              8'b00000110,8'b00001110,8'b00010110,8'b00011110,8'b00100110,8'b00101110,8'b00111110  :
 
                begin
 
                begin
 
                  // LD r,n
 
                  // LD r,n
 
                  MCycles = 3'b010;
 
                  MCycles = 3'b010;
 
                  case (MCycle)
 
                  if (MCycle[1])
 
                        2  :
 
 
 
                          begin
 
                          begin
 
                                Inc_PC = 1'b1;
 
                                Inc_PC = 1'b1;
 
                                Set_BusA_To[2:0] = DDD;
 
                                Set_BusA_To[2:0] = DDD;
 
                                Read_To_Reg = 1'b1;
 
                                Read_To_Reg = 1'b1;
 
                          end
 
                          end
 
                    default :;
 
 
 
                  endcase // case(MCycle)
 
 
 
                end // case: 8'b00000110,8'b00001110,8'b00010110,8'b00011110,8'b00100110,8'b00101110,8'b00111110
 
                end // case: 8'b00000110,8'b00001110,8'b00010110,8'b00011110,8'b00100110,8'b00101110,8'b00111110
 
 
 
 
 
              8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01111110  :
 
              8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01111110  :
 
                  begin
 
                  begin
 
                    // LD r,(HL)
 
                    // LD r,(HL)
 
                    MCycles = 3'b010;
 
                    MCycles = 3'b010;
 
                    case (MCycle)
 
                    if (MCycle[0])
 
                      1  :
 
 
 
                                Set_Addr_To = aXY;
 
                                Set_Addr_To = aXY;
 
                      2  :
 
                    if (MCycle[1])
 
                        begin
 
                        begin
 
                          Set_BusA_To[2:0] = DDD;
 
                          Set_BusA_To[2:0] = DDD;
 
                          Read_To_Reg = 1'b1;
 
                          Read_To_Reg = 1'b1;
 
                        end
 
                        end
 
                      default :;
 
 
 
                    endcase // case(MCycle)
 
 
 
                  end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01111110
 
                  end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01111110
 
 
 
 
 
              8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111  :
 
              8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111  :
 
                  begin
 
                  begin
 
                    // LD (HL),r
 
                    // LD (HL),r
 
                    MCycles = 3'b010;
 
                    MCycles = 3'b010;
 
                    case (MCycle)
 
                    if (MCycle[0])
 
                      1  :
 
 
 
                        begin
 
                        begin
 
                          Set_Addr_To = aXY;
 
                          Set_Addr_To = aXY;
 
                          Set_BusB_To[2:0] = SSS;
 
                          Set_BusB_To[2:0] = SSS;
 
                          Set_BusB_To[3] = 1'b0;
 
                          Set_BusB_To[3] = 1'b0;
 
                        end
 
                        end
 
                      2  :
 
                    if (MCycle[1])
 
                        Write = 1'b1;
 
                        Write = 1'b1;
 
                      default :;
 
 
 
                    endcase // case(MCycle)
 
 
 
                  end // case: 8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111
 
                  end // case: 8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111
 
 
 
 
 
              8'b00110110  :
 
              8'b00110110  :
 
                  begin
 
                  begin
 
                    // LD (HL),n
 
                    // LD (HL),n
 
                    MCycles = 3'b011;
 
                    MCycles = 3'b011;
 
                    case (MCycle)
 
                    if (MCycle[1])
 
                      2  :
 
 
 
                        begin
 
                        begin
 
                          Inc_PC = 1'b1;
 
                          Inc_PC = 1'b1;
 
                          Set_Addr_To = aXY;
 
                          Set_Addr_To = aXY;
 
                          Set_BusB_To[2:0] = SSS;
 
                          Set_BusB_To[2:0] = SSS;
 
                          Set_BusB_To[3] = 1'b0;
 
                          Set_BusB_To[3] = 1'b0;
 
                        end
 
                        end
 
                      3  :
 
                    if (MCycle[2])
 
                        Write = 1'b1;
 
                        Write = 1'b1;
 
                      default :;
 
 
 
                    endcase // case(MCycle)
 
 
 
                  end // case: 8'b00110110
 
                  end // case: 8'b00110110
 
 
 
 
 
              8'b00001010  :
 
              8'b00001010  :
 
                begin
 
                begin
 
                  // LD A,(BC)
 
                  // LD A,(BC)
 
                  MCycles = 3'b010;
 
                  MCycles = 3'b010;
 
                  case (MCycle)
 
                  if (MCycle[0])
 
                    1  :
 
 
 
                      Set_Addr_To = aBC;
 
                      Set_Addr_To = aBC;
 
                    2  :
 
                  if (MCycle[1])
 
                      Read_To_Acc = 1'b1;
 
                      Read_To_Acc = 1'b1;
 
                    default :;
 
 
 
                  endcase // case(MCycle)
 
 
 
                end // case: 8'b00001010
 
                end // case: 8'b00001010
 
 
 
 
 
              8'b00011010  :
 
              8'b00011010  :
 
                begin
 
                begin
 
                  // LD A,(DE)
 
                  // LD A,(DE)
 
                  MCycles = 3'b010;
 
                  MCycles = 3'b010;
 
                  case (MCycle)
 
                  if (MCycle[0])
 
                    1  :
 
 
 
                      Set_Addr_To = aDE;
 
                      Set_Addr_To = aDE;
 
                    2  :
 
                  if (MCycle[1])
 
                      Read_To_Acc = 1'b1;
 
                      Read_To_Acc = 1'b1;
 
                    default :;
 
 
 
                  endcase // case(MCycle)
 
 
 
                end // case: 8'b00011010
 
                end // case: 8'b00011010
 
 
 
 
 
              8'b00111010  :
 
              8'b00111010  :
 
                begin
 
                begin
 
                  if (Mode == 3 )
 
                  if (Mode == 3 )
 
                    begin
 
                    begin
 
                      // LDD A,(HL)
 
                      // LDD A,(HL)
 
                      MCycles = 3'b010;
 
                      MCycles = 3'b010;
 
                      case (MCycle)
 
                      if (MCycle[0])
 
                        1  :
 
 
 
                          Set_Addr_To = aXY;
 
                          Set_Addr_To = aXY;
 
                        2  :
 
                      if (MCycle[1])
 
                          begin
 
                          begin
 
                            Read_To_Acc = 1'b1;
 
                            Read_To_Acc = 1'b1;
 
                            IncDec_16 = 4'b1110;
 
                            IncDec_16 = 4'b1110;
 
                          end
 
                          end
 
                        default :;
 
 
 
                      endcase
 
 
 
                    end
 
                    end
 
                  else
 
                  else
 
                    begin
 
                    begin
 
                      // LD A,(nn)
 
                      // LD A,(nn)
 
                      MCycles = 3'b100;
 
                      MCycles = 3'b100;
 
                      case (MCycle)
 
                      if (MCycle[1])
 
                        2  :
 
 
 
                          begin
 
                          begin
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            LDZ = 1'b1;
 
                            LDZ = 1'b1;
 
                          end
 
                          end
 
                        3  :
 
                      if (MCycle[2])
 
                          begin
 
                          begin
 
                            Set_Addr_To = aZI;
 
                            Set_Addr_To = aZI;
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                          end
 
                          end
 
                        4  :
 
                      if (MCycle[3])
 
                          begin
 
                          begin
 
                            Read_To_Acc = 1'b1;
 
                            Read_To_Acc = 1'b1;
 
                          end
 
                          end
 
                        default :;
 
 
 
                      endcase
 
 
 
                    end // else: !if(Mode == 3 )
 
                    end // else: !if(Mode == 3 )
 
                end // case: 8'b00111010
 
                end // case: 8'b00111010
 
 
 
 
 
              8'b00000010  :
 
              8'b00000010  :
 
                begin
 
                begin
 
                  // LD (BC),A
 
                  // LD (BC),A
 
                  MCycles = 3'b010;
 
                  MCycles = 3'b010;
 
                  case (MCycle)
 
                  if (MCycle[0])
 
                    1  :
 
 
 
                      begin
 
                      begin
 
                        Set_Addr_To = aBC;
 
                        Set_Addr_To = aBC;
 
                        Set_BusB_To = 4'b0111;
 
                        Set_BusB_To = 4'b0111;
 
                      end
 
                      end
 
                    2  :
 
                  if (MCycle[1])
 
                      begin
 
                      begin
 
                        Write = 1'b1;
 
                        Write = 1'b1;
 
                      end
 
                      end
 
                    default :;
 
 
 
                  endcase // case(MCycle)
 
 
 
                end // case: 8'b00000010
 
                end // case: 8'b00000010
 
 
 
 
 
              8'b00010010  :
 
              8'b00010010  :
 
                begin
 
                begin
 
                  // LD (DE),A
 
                  // LD (DE),A
 
                  MCycles = 3'b010;
 
                  MCycles = 3'b010;
 
                  case (MCycle)
 
                  case (1'b1) // MCycle
 
                    1  :
 
                    MCycle[0] :
 
                      begin
 
                      begin
 
                        Set_Addr_To = aDE;
 
                        Set_Addr_To = aDE;
 
                        Set_BusB_To = 4'b0111;
 
                        Set_BusB_To = 4'b0111;
 
                      end
 
                      end
 
                    2  :
 
                    MCycle[1] :
 
                      Write = 1'b1;
 
                      Write = 1'b1;
 
                    default :;
 
                    default :;
 
                  endcase // case(MCycle)
 
                  endcase // case(MCycle)
 
                end // case: 8'b00010010
 
                end // case: 8'b00010010
 
 
 
 
Line 460... Line 433... 
                begin
 
                begin
 
                  if (Mode == 3 )
 
                  if (Mode == 3 )
 
                    begin
 
                    begin
 
                      // LDD (HL),A
 
                      // LDD (HL),A
 
                      MCycles = 3'b010;
 
                      MCycles = 3'b010;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        1  :
 
                        MCycle[0] :
 
                          begin
 
                          begin
 
                            Set_Addr_To = aXY;
 
                            Set_Addr_To = aXY;
 
                            Set_BusB_To = 4'b0111;
 
                            Set_BusB_To = 4'b0111;
 
                          end
 
                          end
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Write = 1'b1;
 
                            Write = 1'b1;
 
                            IncDec_16 = 4'b1110;
 
                            IncDec_16 = 4'b1110;
 
                          end
 
                          end
 
                        default :;
 
                        default :;
Line 479... Line 452... 
                    end
 
                    end
 
                  else
 
                  else
 
                    begin
 
                    begin
 
                      // LD (nn),A
 
                      // LD (nn),A
 
                      MCycles = 3'b100;
 
                      MCycles = 3'b100;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            LDZ = 1'b1;
 
                            LDZ = 1'b1;
 
                          end
 
                          end
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            Set_Addr_To = aZI;
 
                            Set_Addr_To = aZI;
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            Set_BusB_To = 4'b0111;
 
                            Set_BusB_To = 4'b0111;
 
                          end
 
                          end
 
                        4  :
 
                        MCycle[3] :
 
                          begin
 
                          begin
 
                            Write = 1'b1;
 
                            Write = 1'b1;
 
                          end
 
                          end
 
                        default :;
 
                        default :;
 
                      endcase
 
                      endcase
Line 506... Line 479... 
// 16 BIT LOAD GROUP
 
// 16 BIT LOAD GROUP
 
              8'b00000001,8'b00010001,8'b00100001,8'b00110001  :
 
              8'b00000001,8'b00010001,8'b00100001,8'b00110001  :
 
                begin
 
                begin
 
                  // LD dd,nn
 
                  // LD dd,nn
 
                  MCycles = 3'b011;
 
                  MCycles = 3'b011;
 
                  case (MCycle)
 
                  case (1'b1) // MCycle
 
                    2  :
 
                    MCycle[1] :
 
                      begin
 
                      begin
 
                        Inc_PC = 1'b1;
 
                        Inc_PC = 1'b1;
 
                        Read_To_Reg = 1'b1;
 
                        Read_To_Reg = 1'b1;
 
                        if (DPAIR == 2'b11 )
 
                        if (DPAIR == 2'b11 )
 
                          begin
 
                          begin
Line 522... Line 495... 
                            Set_BusA_To[2:1] = DPAIR;
 
                            Set_BusA_To[2:1] = DPAIR;
 
                            Set_BusA_To[0] = 1'b1;
 
                            Set_BusA_To[0] = 1'b1;
 
                          end
 
                          end
 
                      end // case: 2
 
                      end // case: 2
 
 
 
 
 
                    3  :
 
                    MCycle[2] :
 
                      begin
 
                      begin
 
                        Inc_PC = 1'b1;
 
                        Inc_PC = 1'b1;
 
                        Read_To_Reg = 1'b1;
 
                        Read_To_Reg = 1'b1;
 
                        if (DPAIR == 2'b11 )
 
                        if (DPAIR == 2'b11 )
 
                          begin
 
                          begin
Line 547... Line 520... 
                begin
 
                begin
 
                  if (Mode == 3 )
 
                  if (Mode == 3 )
 
                    begin
 
                    begin
 
                      // LDI A,(HL)
 
                      // LDI A,(HL)
 
                      MCycles = 3'b010;
 
                      MCycles = 3'b010;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        1  :
 
                        MCycle[0] :
 
                          Set_Addr_To = aXY;
 
                          Set_Addr_To = aXY;
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Read_To_Acc = 1'b1;
 
                            Read_To_Acc = 1'b1;
 
                            IncDec_16 = 4'b0110;
 
                            IncDec_16 = 4'b0110;
 
                          end
 
                          end
 
 
 
 
Line 563... Line 536... 
                    end
 
                    end
 
                  else
 
                  else
 
                    begin
 
                    begin
 
                      // LD HL,(nn)
 
                      // LD HL,(nn)
 
                      MCycles = 3'b101;
 
                      MCycles = 3'b101;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            LDZ = 1'b1;
 
                            LDZ = 1'b1;
 
                          end
 
                          end
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            Set_Addr_To = aZI;
 
                            Set_Addr_To = aZI;
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            LDW = 1'b1;
 
                            LDW = 1'b1;
 
                          end
 
                          end
 
                        4  :
 
                        MCycle[3] :
 
                          begin
 
                          begin
 
                            Set_BusA_To[2:0] = 3'b101; // L
 
                            Set_BusA_To[2:0] = 3'b101; // L
 
                            Read_To_Reg = 1'b1;
 
                            Read_To_Reg = 1'b1;
 
                            Inc_WZ = 1'b1;
 
                            Inc_WZ = 1'b1;
 
                            Set_Addr_To = aZI;
 
                            Set_Addr_To = aZI;
 
                          end
 
                          end
 
                        5  :
 
                        MCycle[4] :
 
                          begin
 
                          begin
 
                            Set_BusA_To[2:0] = 3'b100; // H
 
                            Set_BusA_To[2:0] = 3'b100; // H
 
                            Read_To_Reg = 1'b1;
 
                            Read_To_Reg = 1'b1;
 
                          end
 
                          end
 
                        default :;
 
                        default :;
Line 598... Line 571... 
                begin
 
                begin
 
                  if (Mode == 3 )
 
                  if (Mode == 3 )
 
                    begin
 
                    begin
 
                      // LDI (HL),A
 
                      // LDI (HL),A
 
                      MCycles = 3'b010;
 
                      MCycles = 3'b010;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        1  :
 
                        MCycle[0] :
 
                          begin
 
                          begin
 
                            Set_Addr_To = aXY;
 
                            Set_Addr_To = aXY;
 
                            Set_BusB_To = 4'b0111;
 
                            Set_BusB_To = 4'b0111;
 
                          end
 
                          end
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Write = 1'b1;
 
                            Write = 1'b1;
 
                            IncDec_16 = 4'b0110;
 
                            IncDec_16 = 4'b0110;
 
                          end
 
                          end
 
                        default :;
 
                        default :;
Line 616... Line 589... 
                    end
 
                    end
 
                  else
 
                  else
 
                    begin
 
                    begin
 
                      // LD (nn),HL
 
                      // LD (nn),HL
 
                      MCycles = 3'b101;
 
                      MCycles = 3'b101;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle                        
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            LDZ = 1'b1;
 
                            LDZ = 1'b1;
 
                          end
 
                          end
 
 
 
 
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            Set_Addr_To = aZI;
 
                            Set_Addr_To = aZI;
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            LDW = 1'b1;
 
                            LDW = 1'b1;
 
                            Set_BusB_To = 4'b0101; // L
 
                            Set_BusB_To = 4'b0101; // L
 
                          end
 
                          end
 
 
 
 
 
                        4  :
 
                        MCycle[3] :
 
                          begin
 
                          begin
 
                            Inc_WZ = 1'b1;
 
                            Inc_WZ = 1'b1;
 
                            Set_Addr_To = aZI;
 
                            Set_Addr_To = aZI;
 
                            Write = 1'b1;
 
                            Write = 1'b1;
 
                            Set_BusB_To = 4'b0100; // H
 
                            Set_BusB_To = 4'b0100; // H
 
                          end
 
                          end
 
                        5  :
 
                        MCycle[4] :
 
                          Write = 1'b1;
 
                          Write = 1'b1;
 
                        default :;
 
                        default :;
 
                      endcase
 
                      endcase
 
                    end // else: !if(Mode == 3 )
 
                    end // else: !if(Mode == 3 )
 
                end // case: 8'b00100010
 
                end // case: 8'b00100010
Line 656... Line 629... 
 
 
 
 
              8'b11000101,8'b11010101,8'b11100101,8'b11110101  :
 
              8'b11000101,8'b11010101,8'b11100101,8'b11110101  :
 
                begin
 
                begin
 
                  // PUSH qq
 
                  // PUSH qq
 
                  MCycles = 3'b011;
 
                  MCycles = 3'b011;
 
                  case (MCycle)
 
                  case (1'b1) // MCycle                    
                    1  :
 
                    MCycle[0] :
 
                      begin
 
                      begin
 
                        TStates = 3'b101;
 
                        TStates = 3'b101;
 
                        IncDec_16 = 4'b1111;
 
                        IncDec_16 = 4'b1111;
 
                        Set_Addr_To = aSP;
 
                        Set_Addr_To = aSP;
 
                        if (DPAIR == 2'b11 )
 
                        if (DPAIR == 2'b11 )
Line 674... Line 647... 
                            Set_BusB_To[0] = 1'b0;
 
                            Set_BusB_To[0] = 1'b0;
 
                            Set_BusB_To[3] = 1'b0;
 
                            Set_BusB_To[3] = 1'b0;
 
                          end
 
                          end
 
                      end // case: 1
 
                      end // case: 1
 
 
 
 
 
                    2  :
 
                    MCycle[1] :
 
                      begin
 
                      begin
 
                        IncDec_16 = 4'b1111;
 
                        IncDec_16 = 4'b1111;
 
                        Set_Addr_To = aSP;
 
                        Set_Addr_To = aSP;
 
                        if (DPAIR == 2'b11 )
 
                        if (DPAIR == 2'b11 )
 
                          begin
 
                          begin
Line 691... Line 664... 
                            Set_BusB_To[3] = 1'b0;
 
                            Set_BusB_To[3] = 1'b0;
 
                          end
 
                          end
 
                        Write = 1'b1;
 
                        Write = 1'b1;
 
                      end // case: 2
 
                      end // case: 2
 
 
 
 
 
                    3  :
 
                    MCycle[2] :
 
                      Write = 1'b1;
 
                      Write = 1'b1;
 
                    default :;
 
                    default :;
 
                  endcase // case(MCycle)
 
                  endcase // case(MCycle)
 
                end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101
 
                end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101
 
 
 
 
 
              8'b11000001,8'b11010001,8'b11100001,8'b11110001  :
 
              8'b11000001,8'b11010001,8'b11100001,8'b11110001  :
 
                begin
 
                begin
 
                  // POP qq
 
                  // POP qq
 
                  MCycles = 3'b011;
 
                  MCycles = 3'b011;
 
                  case (MCycle)
 
                  case (1'b1) // MCycle
 
                    1  :
 
                    MCycle[0] :
 
                      Set_Addr_To = aSP;
 
                      Set_Addr_To = aSP;
 
                    2  :
 
                    MCycle[1] :
 
                      begin
 
                      begin
 
                        IncDec_16 = 4'b0111;
 
                        IncDec_16 = 4'b0111;
 
                        Set_Addr_To = aSP;
 
                        Set_Addr_To = aSP;
 
                        Read_To_Reg = 1'b1;
 
                        Read_To_Reg = 1'b1;
 
                        if (DPAIR == 2'b11 )
 
                        if (DPAIR == 2'b11 )
Line 720... Line 693... 
                            Set_BusA_To[2:1] = DPAIR;
 
                            Set_BusA_To[2:1] = DPAIR;
 
                            Set_BusA_To[0] = 1'b1;
 
                            Set_BusA_To[0] = 1'b1;
 
                          end
 
                          end
 
                      end // case: 2
 
                      end // case: 2
 
 
 
 
 
                    3  :
 
                    MCycle[2] :
 
                      begin
 
                      begin
 
                        IncDec_16 = 4'b0111;
 
                        IncDec_16 = 4'b0111;
 
                        Read_To_Reg = 1'b1;
 
                        Read_To_Reg = 1'b1;
 
                        if (DPAIR == 2'b11 )
 
                        if (DPAIR == 2'b11 )
 
                          begin
 
                          begin
Line 756... Line 729... 
                begin
 
                begin
 
                  if (Mode == 3 )
 
                  if (Mode == 3 )
 
                    begin
 
                    begin
 
                      // LD (nn),SP
 
                      // LD (nn),SP
 
                      MCycles = 3'b101;
 
                      MCycles = 3'b101;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            LDZ = 1'b1;
 
                            LDZ = 1'b1;
 
                          end
 
                          end
 
 
 
 
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            Set_Addr_To = aZI;
 
                            Set_Addr_To = aZI;
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            LDW = 1'b1;
 
                            LDW = 1'b1;
 
                            Set_BusB_To = 4'b1000;
 
                            Set_BusB_To = 4'b1000;
 
                          end
 
                          end
 
 
 
 
 
                        4  :
 
                        MCycle[3] :
 
                          begin
 
                          begin
 
                            Inc_WZ = 1'b1;
 
                            Inc_WZ = 1'b1;
 
                            Set_Addr_To = aZI;
 
                            Set_Addr_To = aZI;
 
                            Write = 1'b1;
 
                            Write = 1'b1;
 
                            Set_BusB_To = 4'b1001;
 
                            Set_BusB_To = 4'b1001;
 
                          end
 
                          end
 
 
 
 
 
                        5  :
 
                        MCycle[4] :
 
                          Write = 1'b1;
 
                          Write = 1'b1;
 
                        default :;
 
                        default :;
 
                      endcase
 
                      endcase
 
                    end
 
                    end
 
                  else if (Mode < 2 )
 
                  else if (Mode < 2 )
Line 797... Line 770... 
                begin
 
                begin
 
                  if (Mode == 3 )
 
                  if (Mode == 3 )
 
                    begin
 
                    begin
 
                      // RETI
 
                      // RETI
 
                      MCycles = 3'b011;
 
                      MCycles = 3'b011;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        1  :
 
                        MCycle[0] :
 
                          Set_Addr_To = aSP;
 
                          Set_Addr_To = aSP;
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            IncDec_16 = 4'b0111;
 
                            IncDec_16 = 4'b0111;
 
                            Set_Addr_To = aSP;
 
                            Set_Addr_To = aSP;
 
                            LDZ = 1'b1;
 
                            LDZ = 1'b1;
 
                          end
 
                          end
 
 
 
 
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            Jump = 1'b1;
 
                            Jump = 1'b1;
 
                            IncDec_16 = 4'b0111;
 
                            IncDec_16 = 4'b0111;
 
                            I_RETN = 1'b1;
 
                            I_RETN = 1'b1;
 
                            SetEI = 1'b1;
 
                            SetEI = 1'b1;
Line 830... Line 803... 
                begin
 
                begin
 
                  if (Mode != 3 )
 
                  if (Mode != 3 )
 
                    begin
 
                    begin
 
                      // EX (SP),HL
 
                      // EX (SP),HL
 
                      MCycles = 3'b101;
 
                      MCycles = 3'b101;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        1  :
 
                        MCycle[0] :
 
                          Set_Addr_To = aSP;
 
                          Set_Addr_To = aSP;
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Read_To_Reg = 1'b1;
 
                            Read_To_Reg = 1'b1;
 
                            Set_BusA_To = 4'b0101;
 
                            Set_BusA_To = 4'b0101;
 
                            Set_BusB_To = 4'b0101;
 
                            Set_BusB_To = 4'b0101;
 
                            Set_Addr_To = aSP;
 
                            Set_Addr_To = aSP;
 
                          end
 
                          end
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            IncDec_16 = 4'b0111;
 
                            IncDec_16 = 4'b0111;
 
                            Set_Addr_To = aSP;
 
                            Set_Addr_To = aSP;
 
                            TStates = 3'b100;
 
                            TStates = 3'b100;
 
                            Write = 1'b1;
 
                            Write = 1'b1;
 
                          end
 
                          end
 
                        4  :
 
                        MCycle[3] :
 
                          begin
 
                          begin
 
                            Read_To_Reg = 1'b1;
 
                            Read_To_Reg = 1'b1;
 
                            Set_BusA_To = 4'b0100;
 
                            Set_BusA_To = 4'b0100;
 
                            Set_BusB_To = 4'b0100;
 
                            Set_BusB_To = 4'b0100;
 
                            Set_Addr_To = aSP;
 
                            Set_Addr_To = aSP;
 
                          end
 
                          end
 
                        5  :
 
                        MCycle[4] :
 
                          begin
 
                          begin
 
                            IncDec_16 = 4'b1111;
 
                            IncDec_16 = 4'b1111;
 
                            TStates = 3'b101;
 
                            TStates = 3'b101;
 
                            Write = 1'b1;
 
                            Write = 1'b1;
 
                          end
 
                          end
Line 902... Line 875... 
                  // AND A,(HL)
 
                  // AND A,(HL)
 
                  // OR A,(HL)
 
                  // OR A,(HL)
 
                  // XOR A,(HL)
 
                  // XOR A,(HL)
 
                  // CP A,(HL)
 
                  // CP A,(HL)
 
                  MCycles = 3'b010;
 
                  MCycles = 3'b010;
 
                  case (MCycle)
 
                  case (1'b1) // MCycle
 
                    1  :
 
                    MCycle[0] :
 
                      Set_Addr_To = aXY;
 
                      Set_Addr_To = aXY;
 
                    2  :
 
                    MCycle[1] :
 
                      begin
 
                      begin
 
                        Read_To_Reg = 1'b1;
 
                        Read_To_Reg = 1'b1;
 
                        Save_ALU = 1'b1;
 
                        Save_ALU = 1'b1;
 
                        Set_BusB_To[2:0] = SSS;
 
                        Set_BusB_To[2:0] = SSS;
 
                        Set_BusA_To[2:0] = 3'b111;
 
                        Set_BusA_To[2:0] = 3'b111;
Line 953... Line 926... 
 
 
 
 
              8'b00110100  :
 
              8'b00110100  :
 
                begin
 
                begin
 
                  // INC (HL)
 
                  // INC (HL)
 
                  MCycles = 3'b011;
 
                  MCycles = 3'b011;
 
                  case (MCycle)
 
                  case (1'b1) // MCycle
 
                    1  :
 
                    MCycle[0] :
 
                      Set_Addr_To = aXY;
 
                      Set_Addr_To = aXY;
 
                    2  :
 
                    MCycle[1] :
 
                      begin
 
                      begin
 
                        TStates = 3'b100;
 
                        TStates = 3'b100;
 
                        Set_Addr_To = aXY;
 
                        Set_Addr_To = aXY;
 
                        Read_To_Reg = 1'b1;
 
                        Read_To_Reg = 1'b1;
 
                        Save_ALU = 1'b1;
 
                        Save_ALU = 1'b1;
Line 968... Line 941... 
                        ALU_Op = 4'b0000;
 
                        ALU_Op = 4'b0000;
 
                        Set_BusB_To = 4'b1010;
 
                        Set_BusB_To = 4'b1010;
 
                        Set_BusA_To[2:0] = DDD;
 
                        Set_BusA_To[2:0] = DDD;
 
                      end // case: 2
 
                      end // case: 2
 
 
 
 
 
                    3  :
 
                    MCycle[2] :
 
                      Write = 1'b1;
 
                      Write = 1'b1;
 
                    default :;
 
                    default :;
 
                  endcase // case(MCycle)
 
                  endcase // case(MCycle)
 
                end // case: 8'b00110100
 
                end // case: 8'b00110100
 
 
 
 
Line 989... Line 962... 
 
 
 
 
              8'b00110101  :
 
              8'b00110101  :
 
                begin
 
                begin
 
                  // DEC (HL)
 
                  // DEC (HL)
 
                  MCycles = 3'b011;
 
                  MCycles = 3'b011;
 
                  case (MCycle)
 
                  case (1'b1) // MCycle
 
                    1  :
 
                    MCycle[0] :
 
                      Set_Addr_To = aXY;
 
                      Set_Addr_To = aXY;
 
                    2  :
 
                    MCycle[1] :
 
                      begin
 
                      begin
 
                        TStates = 3'b100;
 
                        TStates = 3'b100;
 
                        Set_Addr_To = aXY;
 
                        Set_Addr_To = aXY;
 
                        ALU_Op = 4'b0010;
 
                        ALU_Op = 4'b0010;
 
                        Read_To_Reg = 1'b1;
 
                        Read_To_Reg = 1'b1;
Line 1004... Line 977... 
                        PreserveC = 1'b1;
 
                        PreserveC = 1'b1;
 
                        Set_BusB_To = 4'b1010;
 
                        Set_BusB_To = 4'b1010;
 
                        Set_BusA_To[2:0] = DDD;
 
                        Set_BusA_To[2:0] = DDD;
 
                      end // case: 2
 
                      end // case: 2
 
 
 
 
 
                    3  :
 
                    MCycle[2] :
 
                      Write = 1'b1;
 
                      Write = 1'b1;
 
                    default :;
 
                    default :;
 
                  endcase // case(MCycle)
 
                  endcase // case(MCycle)
 
                end // case: 8'b00110101              
                end // case: 8'b00110101              
 
 
 
Line 1038... Line 1011... 
                  begin
 
                  begin
 
                    if (NMICycle == 1'b1 )
 
                    if (NMICycle == 1'b1 )
 
                      begin
 
                      begin
 
                        // NMI
 
                        // NMI
 
                        MCycles = 3'b011;
 
                        MCycles = 3'b011;
 
                        case (MCycle)
 
                        case (1'b1) // MCycle
 
                          1  :
 
                          MCycle[0] :
 
                            begin
 
                            begin
 
                              TStates = 3'b101;
 
                              TStates = 3'b101;
 
                              IncDec_16 = 4'b1111;
 
                              IncDec_16 = 4'b1111;
 
                              Set_Addr_To = aSP;
 
                              Set_Addr_To = aSP;
 
                              Set_BusB_To = 4'b1101;
 
                              Set_BusB_To = 4'b1101;
 
                            end
 
                            end
 
 
 
 
 
                          2  :
 
                          MCycle[1] :
 
                            begin
 
                            begin
 
                              TStates = 3'b100;
 
                              TStates = 3'b100;
 
                              Write = 1'b1;
 
                              Write = 1'b1;
 
                              IncDec_16 = 4'b1111;
 
                              IncDec_16 = 4'b1111;
 
                              Set_Addr_To = aSP;
 
                              Set_Addr_To = aSP;
 
                              Set_BusB_To = 4'b1100;
 
                              Set_BusB_To = 4'b1100;
 
                            end
 
                            end
 
 
 
 
 
                          3  :
 
                          MCycle[2] :
 
                            begin
 
                            begin
 
                              TStates = 3'b100;
 
                              TStates = 3'b100;
 
                              Write = 1'b1;
 
                              Write = 1'b1;
 
                            end
 
                            end
 
 
 
 
Line 1070... Line 1043... 
                      end
 
                      end
 
                    else if (IntCycle == 1'b1 )
 
                    else if (IntCycle == 1'b1 )
 
                      begin
 
                      begin
 
                        // INT (IM 2)
 
                        // INT (IM 2)
 
                        MCycles = 3'b101;
 
                        MCycles = 3'b101;
 
                        case (MCycle)
 
                        case (1'b1) // MCycle
 
                          1  :
 
                          MCycle[0] :
 
                            begin
 
                            begin
 
                              LDZ = 1'b1;
 
                              LDZ = 1'b1;
 
                              TStates = 3'b101;
 
                              TStates = 3'b101;
 
                              IncDec_16 = 4'b1111;
 
                              IncDec_16 = 4'b1111;
 
                              Set_Addr_To = aSP;
 
                              Set_Addr_To = aSP;
 
                              Set_BusB_To = 4'b1101;
 
                              Set_BusB_To = 4'b1101;
 
                            end
 
                            end
 
 
 
 
 
                          2  :
 
                          MCycle[1] :
 
                            begin
 
                            begin
 
                              TStates = 3'b100;
 
                              TStates = 3'b100;
 
                              Write = 1'b1;
 
                              Write = 1'b1;
 
                              IncDec_16 = 4'b1111;
 
                              IncDec_16 = 4'b1111;
 
                              Set_Addr_To = aSP;
 
                              Set_Addr_To = aSP;
 
                              Set_BusB_To = 4'b1100;
 
                              Set_BusB_To = 4'b1100;
 
                            end
 
                            end
 
 
 
 
 
                          3  :
 
                          MCycle[2] :
 
                            begin
 
                            begin
 
                              TStates = 3'b100;
 
                              TStates = 3'b100;
 
                              Write = 1'b1;
 
                              Write = 1'b1;
 
                            end
 
                            end
 
 
 
 
 
                          4  :
 
                          MCycle[3] :
 
                            begin
 
                            begin
 
                              Inc_PC = 1'b1;
 
                              Inc_PC = 1'b1;
 
                              LDZ = 1'b1;
 
                              LDZ = 1'b1;
 
                            end
 
                            end
 
 
 
 
 
                          5  :
 
                          MCycle[4] :
 
                            Jump = 1'b1;
 
                            Jump = 1'b1;
 
                          default :;
 
                          default :;
 
                        endcase
 
                        endcase
 
                      end
 
                      end
 
                  end // case: 8'b00000000
 
                  end // case: 8'b00000000
Line 1125... Line 1098... 
              // 16 BIT ARITHMETIC GROUP
 
              // 16 BIT ARITHMETIC GROUP
 
              8'b00001001,8'b00011001,8'b00101001,8'b00111001  :
 
              8'b00001001,8'b00011001,8'b00101001,8'b00111001  :
 
                begin
 
                begin
 
                  // ADD HL,ss
 
                  // ADD HL,ss
 
                  MCycles = 3'b011;
 
                  MCycles = 3'b011;
 
                  case (MCycle)
 
                  case (1'b1) // MCycle
 
                    2  :
 
                    MCycle[1] :
 
                      begin
 
                      begin
 
                        NoRead = 1'b1;
 
                        NoRead = 1'b1;
 
                        ALU_Op = 4'b0000;
 
                        ALU_Op = 4'b0000;
 
                        Read_To_Reg = 1'b1;
 
                        Read_To_Reg = 1'b1;
 
                        Save_ALU = 1'b1;
 
                        Save_ALU = 1'b1;
Line 1148... Line 1121... 
 
 
 
 
                        TStates = 3'b100;
 
                        TStates = 3'b100;
 
                        Arith16 = 1'b1;
 
                        Arith16 = 1'b1;
 
                      end // case: 2
 
                      end // case: 2
 
 
 
 
 
                    3  :
 
                    MCycle[2] :
 
                      begin
 
                      begin
 
                        NoRead = 1'b1;
 
                        NoRead = 1'b1;
 
                        Read_To_Reg = 1'b1;
 
                        Read_To_Reg = 1'b1;
 
                        Save_ALU = 1'b1;
 
                        Save_ALU = 1'b1;
 
                        ALU_Op = 4'b0001;
 
                        ALU_Op = 4'b0001;
Line 1206... Line 1179... 
// JUMP GROUP
 
// JUMP GROUP
 
              8'b11000011  :
 
              8'b11000011  :
 
                begin
 
                begin
 
                  // JP nn
 
                  // JP nn
 
                  MCycles = 3'b011;
 
                  MCycles = 3'b011;
 
                  case (MCycle)
 
                  if (MCycle[1])
 
                    2  :
 
 
 
                      begin
 
                      begin
 
                        Inc_PC = 1'b1;
 
                        Inc_PC = 1'b1;
 
                        LDZ = 1'b1;
 
                        LDZ = 1'b1;
 
                      end
 
                      end
 
 
 
 
 
                    3  :
 
                  if (MCycle[2])
 
                      begin
 
                      begin
 
                        Inc_PC = 1'b1;
 
                        Inc_PC = 1'b1;
 
                        Jump = 1'b1;
 
                        Jump = 1'b1;
 
                      end
 
                      end
 
 
 
 
 
                    default :;
 
 
 
                  endcase // case(MCycle)
 
 
 
                end // case: 8'b11000011
 
                end // case: 8'b11000011
 
 
 
 
 
              8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010  :
 
              8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010  :
 
                begin
 
                begin
 
                  if (IR[5] == 1'b1 && Mode == 3 )
 
                  if (IR[5] == 1'b1 && Mode == 3 )
Line 1232... Line 1202... 
                      case (IRB[4:3])
 
                      case (IRB[4:3])
 
                        2'b00  :
 
                        2'b00  :
 
                          begin
 
                          begin
 
                            // LD ($FF00+C),A
 
                            // LD ($FF00+C),A
 
                            MCycles = 3'b010;
 
                            MCycles = 3'b010;
 
                            case (MCycle)
 
                            case (1'b1) // MCycle
 
                              1  :
 
                              MCycle[0] :
 
                                begin
 
                                begin
 
                                  Set_Addr_To = aBC;
 
                                  Set_Addr_To = aBC;
 
                                  Set_BusB_To   = 4'b0111;
 
                                  Set_BusB_To   = 4'b0111;
 
                                end
 
                                end
 
                              2  :
 
                              MCycle[1] :
 
                                begin
 
                                begin
 
                                  Write = 1'b1;
 
                                  Write = 1'b1;
 
                                  IORQ = 1'b1;
 
                                  IORQ = 1'b1;
 
                                end
 
                                end
 
 
 
 
Line 1252... Line 1222... 
 
 
 
 
                        2'b01  :
 
                        2'b01  :
 
                          begin
 
                          begin
 
                            // LD (nn),A
 
                            // LD (nn),A
 
                            MCycles = 3'b100;
 
                            MCycles = 3'b100;
 
                            case (MCycle)
 
                            case (1'b1) // MCycle
 
                              2  :
 
                              MCycle[1] :
 
                                begin
 
                                begin
 
                                  Inc_PC = 1'b1;
 
                                  Inc_PC = 1'b1;
 
                                  LDZ = 1'b1;
 
                                  LDZ = 1'b1;
 
                                end
 
                                end
 
 
 
 
 
                              3  :
 
                              MCycle[2] :
 
                                begin
 
                                begin
 
                                  Set_Addr_To = aZI;
 
                                  Set_Addr_To = aZI;
 
                                  Inc_PC = 1'b1;
 
                                  Inc_PC = 1'b1;
 
                                  Set_BusB_To = 4'b0111;
 
                                  Set_BusB_To = 4'b0111;
 
                                end
 
                                end
 
 
 
 
 
                              4  :
 
                              MCycle[3] :
 
                                Write = 1'b1;
 
                                Write = 1'b1;
 
                              default :;
 
                              default :;
 
                            endcase // case(MCycle)
 
                            endcase // case(MCycle)
 
                          end // case: default :...
 
                          end // case: default :...
 
 
 
 
 
                        2'b10  :
 
                        2'b10  :
 
                          begin
 
                          begin
 
                            // LD A,($FF00+C)
 
                            // LD A,($FF00+C)
 
                            MCycles = 3'b010;
 
                            MCycles = 3'b010;
 
                            case (MCycle)
 
                            case (1'b1) // MCycle
 
                              1  :
 
                              MCycle[0] :
 
                                Set_Addr_To = aBC;
 
                                Set_Addr_To = aBC;
 
                              2  :
 
                              MCycle[1] :
 
                                begin
 
                                begin
 
                                  Read_To_Acc = 1'b1;
 
                                  Read_To_Acc = 1'b1;
 
                                  IORQ = 1'b1;
 
                                  IORQ = 1'b1;
 
                                end
 
                                end
 
                              default :;
 
                              default :;
Line 1292... Line 1262... 
 
 
 
 
                        2'b11  :
 
                        2'b11  :
 
                          begin
 
                          begin
 
                            // LD A,(nn)
 
                            // LD A,(nn)
 
                            MCycles = 3'b100;
 
                            MCycles = 3'b100;
 
                            case (MCycle)
 
                            case (1'b1) // MCycle
 
                              2  :
 
                              MCycle[1] :
 
                                begin
 
                                begin
 
                                  Inc_PC = 1'b1;
 
                                  Inc_PC = 1'b1;
 
                                  LDZ = 1'b1;
 
                                  LDZ = 1'b1;
 
                                end
 
                                end
 
                              3  :
 
                              MCycle[2] :
 
                                begin
 
                                begin
 
                                  Set_Addr_To = aZI;
 
                                  Set_Addr_To = aZI;
 
                                  Inc_PC = 1'b1;
 
                                  Inc_PC = 1'b1;
 
                                end
 
                                end
 
                              4  :
 
                              MCycle[3] :
 
                                Read_To_Acc = 1'b1;
 
                                Read_To_Acc = 1'b1;
 
                              default :;
 
                              default :;
 
                            endcase // case(MCycle)
 
                            endcase // case(MCycle)
 
                          end
 
                          end
 
                      endcase
 
                      endcase
 
                    end
 
                    end
 
                  else
 
                  else
 
                    begin
 
                    begin
 
                      // JP cc,nn
 
                      // JP cc,nn
 
                      MCycles = 3'b011;
 
                      MCycles = 3'b011;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            LDZ = 1'b1;
 
                            LDZ = 1'b1;
 
                          end
 
                          end
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            if (is_cc_true(F, IR[5:3]) )
 
                            if (is_cc_true(F, IR[5:3]) )
 
                              begin
 
                              begin
 
                                Jump = 1'b1;
 
                                Jump = 1'b1;
Line 1340... Line 1310... 
                begin
 
                begin
 
                  if (Mode != 2 )
 
                  if (Mode != 2 )
 
                    begin
 
                    begin
 
                      // JR e
 
                      // JR e
 
                      MCycles = 3'b011;
 
                      MCycles = 3'b011;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        2  :
 
                        MCycle[1] :
 
                          Inc_PC = 1'b1;
 
                          Inc_PC = 1'b1;
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            NoRead = 1'b1;
 
                            NoRead = 1'b1;
 
                            JumpE = 1'b1;
 
                            JumpE = 1'b1;
 
                            TStates = 3'b101;
 
                            TStates = 3'b101;
 
                          end
 
                          end
Line 1360... Line 1330... 
                begin
 
                begin
 
                  if (Mode != 2 )
 
                  if (Mode != 2 )
 
                    begin
 
                    begin
 
                      // JR C,e
 
                      // JR C,e
 
                      MCycles = 3'b011;
 
                      MCycles = 3'b011;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            if (F[Flag_C] == 1'b0 )
 
                            if (F[Flag_C] == 1'b0 )
 
                              begin
 
                              begin
 
                                MCycles = 3'b010;
 
                                MCycles = 3'b010;
 
                              end
 
                              end
 
                          end
 
                          end
 
 
 
 
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            NoRead = 1'b1;
 
                            NoRead = 1'b1;
 
                            JumpE = 1'b1;
 
                            JumpE = 1'b1;
 
                            TStates = 3'b101;
 
                            TStates = 3'b101;
 
                          end
 
                          end
Line 1387... Line 1357... 
                begin
 
                begin
 
                  if (Mode != 2 )
 
                  if (Mode != 2 )
 
                    begin
 
                    begin
 
                      // JR NC,e
 
                      // JR NC,e
 
                      MCycles = 3'b011;
 
                      MCycles = 3'b011;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            if (F[Flag_C] == 1'b1 )
 
                            if (F[Flag_C] == 1'b1 )
 
                              begin
 
                              begin
 
                                MCycles = 3'b010;
 
                                MCycles = 3'b010;
 
                              end
 
                              end
 
                          end
 
                          end
 
 
 
 
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            NoRead = 1'b1;
 
                            NoRead = 1'b1;
 
                            JumpE = 1'b1;
 
                            JumpE = 1'b1;
 
                            TStates = 3'b101;
 
                            TStates = 3'b101;
 
                          end
 
                          end
Line 1414... Line 1384... 
                begin
 
                begin
 
                  if (Mode != 2 )
 
                  if (Mode != 2 )
 
                    begin
 
                    begin
 
                      // JR Z,e
 
                      // JR Z,e
 
                      MCycles = 3'b011;
 
                      MCycles = 3'b011;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            if (F[Flag_Z] == 1'b0 )
 
                            if (F[Flag_Z] == 1'b0 )
 
                              begin
 
                              begin
 
                                MCycles = 3'b010;
 
                                MCycles = 3'b010;
 
                              end
 
                              end
 
                          end
 
                          end
 
 
 
 
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            NoRead = 1'b1;
 
                            NoRead = 1'b1;
 
                            JumpE = 1'b1;
 
                            JumpE = 1'b1;
 
                            TStates = 3'b101;
 
                            TStates = 3'b101;
 
                          end
 
                          end
Line 1442... Line 1412... 
                begin
 
                begin
 
                  if (Mode != 2 )
 
                  if (Mode != 2 )
 
                    begin
 
                    begin
 
                      // JR NZ,e
 
                      // JR NZ,e
 
                      MCycles = 3'b011;
 
                      MCycles = 3'b011;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            if (F[Flag_Z] == 1'b1 )
 
                            if (F[Flag_Z] == 1'b1 )
 
                              begin
 
                              begin
 
                                MCycles = 3'b010;
 
                                MCycles = 3'b010;
 
                              end
 
                              end
 
                          end
 
                          end
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            NoRead = 1'b1;
 
                            NoRead = 1'b1;
 
                            JumpE = 1'b1;
 
                            JumpE = 1'b1;
 
                            TStates = 3'b101;
 
                            TStates = 3'b101;
 
                          end
 
                          end
Line 1476... Line 1446... 
                    end
 
                    end
 
                  else if (Mode < 2 )
 
                  else if (Mode < 2 )
 
                    begin
 
                    begin
 
                      // DJNZ,e
 
                      // DJNZ,e
 
                      MCycles = 3'b011;
 
                      MCycles = 3'b011;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        1  :
 
                        MCycle[0] :
 
                          begin
 
                          begin
 
                            TStates = 3'b101;
 
                            TStates = 3'b101;
 
                            I_DJNZ = 1'b1;
 
                            I_DJNZ = 1'b1;
 
                            Set_BusB_To = 4'b1010;
 
                            Set_BusB_To = 4'b1010;
 
                            Set_BusA_To[2:0] = 3'b000;
 
                            Set_BusA_To[2:0] = 3'b000;
 
                            Read_To_Reg = 1'b1;
 
                            Read_To_Reg = 1'b1;
 
                            Save_ALU = 1'b1;
 
                            Save_ALU = 1'b1;
 
                            ALU_Op = 4'b0010;
 
                            ALU_Op = 4'b0010;
 
                          end
 
                          end
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            I_DJNZ = 1'b1;
 
                            I_DJNZ = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                          end
 
                          end
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            NoRead = 1'b1;
 
                            NoRead = 1'b1;
 
                            JumpE = 1'b1;
 
                            JumpE = 1'b1;
 
                            TStates = 3'b101;
 
                            TStates = 3'b101;
 
                          end
 
                          end
Line 1509... Line 1479... 
// CALL AND RETURN GROUP
 
// CALL AND RETURN GROUP
 
              8'b11001101  :
 
              8'b11001101  :
 
                begin
 
                begin
 
                  // CALL nn
 
                  // CALL nn
 
                  MCycles = 3'b101;
 
                  MCycles = 3'b101;
 
                  case (MCycle)
 
                  case (1'b1) // MCycle
 
                    2  :
 
                    MCycle[1] :
 
                      begin
 
                      begin
 
                        Inc_PC = 1'b1;
 
                        Inc_PC = 1'b1;
 
                        LDZ = 1'b1;
 
                        LDZ = 1'b1;
 
                      end
 
                      end
 
                    3  :
 
                    MCycle[2] :
 
                      begin
 
                      begin
 
                        IncDec_16 = 4'b1111;
 
                        IncDec_16 = 4'b1111;
 
                        Inc_PC = 1'b1;
 
                        Inc_PC = 1'b1;
 
                        TStates = 3'b100;
 
                        TStates = 3'b100;
 
                        Set_Addr_To = aSP;
 
                        Set_Addr_To = aSP;
 
                        LDW = 1'b1;
 
                        LDW = 1'b1;
 
                        Set_BusB_To = 4'b1101;
 
                        Set_BusB_To = 4'b1101;
 
                      end
 
                      end
 
                    4  :
 
                    MCycle[3] :
 
                      begin
 
                      begin
 
                        Write = 1'b1;
 
                        Write = 1'b1;
 
                        IncDec_16 = 4'b1111;
 
                        IncDec_16 = 4'b1111;
 
                        Set_Addr_To = aSP;
 
                        Set_Addr_To = aSP;
 
                        Set_BusB_To = 4'b1100;
 
                        Set_BusB_To = 4'b1100;
 
                      end
 
                      end
 
                    5  :
 
                    MCycle[4] :
 
                      begin
 
                      begin
 
                        Write = 1'b1;
 
                        Write = 1'b1;
 
                        Call = 1'b1;
 
                        Call = 1'b1;
 
                      end
 
                      end
 
                    default :;
 
                    default :;
Line 1546... Line 1516... 
                begin
 
                begin
 
                  if (IR[5] == 1'b0 || Mode != 3 )
 
                  if (IR[5] == 1'b0 || Mode != 3 )
 
                    begin
 
                    begin
 
                      // CALL cc,nn
 
                      // CALL cc,nn
 
                      MCycles = 3'b101;
 
                      MCycles = 3'b101;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            LDZ = 1'b1;
 
                            LDZ = 1'b1;
 
                          end
 
                          end
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            LDW = 1'b1;
 
                            LDW = 1'b1;
 
                            if (is_cc_true(F, IR[5:3]) )
 
                            if (is_cc_true(F, IR[5:3]) )
 
                              begin
 
                              begin
Line 1569... Line 1539... 
                              begin
 
                              begin
 
                                MCycles = 3'b011;
 
                                MCycles = 3'b011;
 
                              end // else: !if(is_cc_true(F, IR[5:3]) )
 
                              end // else: !if(is_cc_true(F, IR[5:3]) )
 
                          end // case: 3
 
                          end // case: 3
 
 
 
 
 
                        4  :
 
                        MCycle[3] :
 
                          begin
 
                          begin
 
                            Write = 1'b1;
 
                            Write = 1'b1;
 
                            IncDec_16 = 4'b1111;
 
                            IncDec_16 = 4'b1111;
 
                            Set_Addr_To = aSP;
 
                            Set_Addr_To = aSP;
 
                            Set_BusB_To = 4'b1100;
 
                            Set_BusB_To = 4'b1100;
 
                          end
 
                          end
 
 
 
 
 
                        5  :
 
                        MCycle[4] :
 
                          begin
 
                          begin
 
                            Write = 1'b1;
 
                            Write = 1'b1;
 
                            Call = 1'b1;
 
                            Call = 1'b1;
 
                          end
 
                          end
 
 
 
 
Line 1592... Line 1562... 
 
 
 
 
              8'b11001001  :
 
              8'b11001001  :
 
                begin
 
                begin
 
                  // RET
 
                  // RET
 
                  MCycles = 3'b011;
 
                  MCycles = 3'b011;
 
                  case (MCycle)
 
                  case (1'b1) // MCycle
 
                    1  :
 
                    MCycle[0] :
 
                      begin
 
                      begin
 
                        TStates = 3'b101;
 
                        TStates = 3'b101;
 
                        Set_Addr_To = aSP;
 
                        Set_Addr_To = aSP;
 
                      end
 
                      end
 
 
 
 
 
                    2  :
 
                    MCycle[1] :
 
                      begin
 
                      begin
 
                        IncDec_16 = 4'b0111;
 
                        IncDec_16 = 4'b0111;
 
                        Set_Addr_To = aSP;
 
                        Set_Addr_To = aSP;
 
                        LDZ = 1'b1;
 
                        LDZ = 1'b1;
 
                      end
 
                      end
 
 
 
 
 
                    3  :
 
                    MCycle[2] :
 
                      begin
 
                      begin
 
                        Jump = 1'b1;
 
                        Jump = 1'b1;
 
                        IncDec_16 = 4'b0111;
 
                        IncDec_16 = 4'b0111;
 
                      end
 
                      end
 
 
 
 
Line 1625... Line 1595... 
                      case (IRB[4:3])
 
                      case (IRB[4:3])
 
                        2'b00  :
 
                        2'b00  :
 
                          begin
 
                          begin
 
                            // LD ($FF00+nn),A
 
                            // LD ($FF00+nn),A
 
                            MCycles = 3'b011;
 
                            MCycles = 3'b011;
 
                            case (MCycle)
 
                            case (1'b1) // MCycle
 
                              2  :
 
                              MCycle[1] :
 
                                begin
 
                                begin
 
                                  Inc_PC = 1'b1;
 
                                  Inc_PC = 1'b1;
 
                                  Set_Addr_To = aIOA;
 
                                  Set_Addr_To = aIOA;
 
                                  Set_BusB_To   = 4'b0111;
 
                                  Set_BusB_To   = 4'b0111;
 
                                end
 
                                end
 
 
 
 
 
                              3  :
 
                              MCycle[2] :
 
                                Write = 1'b1;
 
                                Write = 1'b1;
 
                              default :;
 
                              default :;
 
                            endcase // case(MCycle)
 
                            endcase // case(MCycle)
 
                          end // case: 2'b00
 
                          end // case: 2'b00
 
 
 
 
 
                        2'b01  :
 
                        2'b01  :
 
                          begin
 
                          begin
 
                            // ADD SP,n
 
                            // ADD SP,n
 
                            MCycles = 3'b011;
 
                            MCycles = 3'b011;
 
                            case (MCycle)
 
                            case (1'b1) // MCycle
 
                              2  :
 
                              MCycle[1] :
 
                                begin
 
                                begin
 
                                  ALU_Op = 4'b0000;
 
                                  ALU_Op = 4'b0000;
 
                                  Inc_PC = 1'b1;
 
                                  Inc_PC = 1'b1;
 
                                  Read_To_Reg = 1'b1;
 
                                  Read_To_Reg = 1'b1;
 
                                  Save_ALU = 1'b1;
 
                                  Save_ALU = 1'b1;
 
                                  Set_BusA_To = 4'b1000;
 
                                  Set_BusA_To = 4'b1000;
 
                                  Set_BusB_To = 4'b0110;
 
                                  Set_BusB_To = 4'b0110;
 
                                end
 
                                end
 
 
 
 
 
                              3  :
 
                              MCycle[2] :
 
                                begin
 
                                begin
 
                                  NoRead = 1'b1;
 
                                  NoRead = 1'b1;
 
                                  Read_To_Reg = 1'b1;
 
                                  Read_To_Reg = 1'b1;
 
                                  Save_ALU = 1'b1;
 
                                  Save_ALU = 1'b1;
 
                                  ALU_Op = 4'b0001;
 
                                  ALU_Op = 4'b0001;
Line 1672... Line 1642... 
 
 
 
 
                        2'b10  :
 
                        2'b10  :
 
                          begin
 
                          begin
 
                            // LD A,($FF00+nn)
 
                            // LD A,($FF00+nn)
 
                            MCycles = 3'b011;
 
                            MCycles = 3'b011;
 
                            case (MCycle)
 
                            case (1'b1) // MCycle
 
                              2  :
 
                              MCycle[1] :
 
                                begin
 
                                begin
 
                                  Inc_PC = 1'b1;
 
                                  Inc_PC = 1'b1;
 
                                  Set_Addr_To = aIOA;
 
                                  Set_Addr_To = aIOA;
 
                                end
 
                                end
 
 
 
 
 
                              3  :
 
                              MCycle[2] :
 
                                Read_To_Acc = 1'b1;
 
                                Read_To_Acc = 1'b1;
 
                              default :;
 
                              default :;
 
                            endcase // case(MCycle)
 
                            endcase // case(MCycle)
 
                          end // case: 2'b10
 
                          end // case: 2'b10
 
 
 
 
 
                        2'b11  :
 
                        2'b11  :
 
                          begin
 
                          begin
 
                            // LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
 
                            // LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
 
                            MCycles = 3'b101;
 
                            MCycles = 3'b101;
 
                            case (MCycle)
 
                            case (1'b1) // MCycle
 
                              2  :
 
                              MCycle[1] :
 
                                begin
 
                                begin
 
                                  Inc_PC = 1'b1;
 
                                  Inc_PC = 1'b1;
 
                                  LDZ = 1'b1;
 
                                  LDZ = 1'b1;
 
                                end
 
                                end
 
 
 
 
 
                              3  :
 
                              MCycle[2] :
 
                                begin
 
                                begin
 
                                  Set_Addr_To = aZI;
 
                                  Set_Addr_To = aZI;
 
                                  Inc_PC = 1'b1;
 
                                  Inc_PC = 1'b1;
 
                                  LDW = 1'b1;
 
                                  LDW = 1'b1;
 
                                end
 
                                end
 
 
 
 
 
                              4  :
 
                              MCycle[3] :
 
                                begin
 
                                begin
 
                                  Set_BusA_To[2:0] = 3'b101; // L
 
                                  Set_BusA_To[2:0] = 3'b101; // L
 
                                  Read_To_Reg = 1'b1;
 
                                  Read_To_Reg = 1'b1;
 
                                  Inc_WZ = 1'b1;
 
                                  Inc_WZ = 1'b1;
 
                                  Set_Addr_To = aZI;
 
                                  Set_Addr_To = aZI;
 
                                end
 
                                end
 
 
 
 
 
                              5  :
 
                              MCycle[4] :
 
                                begin
 
                                begin
 
                                  Set_BusA_To[2:0] = 3'b100; // H
 
                                  Set_BusA_To[2:0] = 3'b100; // H
 
                                  Read_To_Reg = 1'b1;
 
                                  Read_To_Reg = 1'b1;
 
                                end
 
                                end
 
 
 
 
Line 1728... Line 1698... 
                    end
 
                    end
 
                  else
 
                  else
 
                    begin
 
                    begin
 
                      // RET cc
 
                      // RET cc
 
                      MCycles = 3'b011;
 
                      MCycles = 3'b011;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        1  :
 
                        MCycle[0] :
 
                          begin
 
                          begin
 
                            if (is_cc_true(F, IR[5:3]) )
 
                            if (is_cc_true(F, IR[5:3]) )
 
                              begin
 
                              begin
 
                                Set_Addr_To = aSP;
 
                                Set_Addr_To = aSP;
 
                              end
 
                              end
Line 1742... Line 1712... 
                                MCycles = 3'b001;
 
                                MCycles = 3'b001;
 
                              end
 
                              end
 
                            TStates = 3'b101;
 
                            TStates = 3'b101;
 
                          end // case: 1
 
                          end // case: 1
 
 
 
 
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            IncDec_16 = 4'b0111;
 
                            IncDec_16 = 4'b0111;
 
                            Set_Addr_To = aSP;
 
                            Set_Addr_To = aSP;
 
                            LDZ = 1'b1;
 
                            LDZ = 1'b1;
 
                          end
 
                          end
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            Jump = 1'b1;
 
                            Jump = 1'b1;
 
                            IncDec_16 = 4'b0111;
 
                            IncDec_16 = 4'b0111;
 
                          end
 
                          end
 
                        default :;
 
                        default :;
Line 1762... Line 1732... 
 
 
 
 
              8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111  :
 
              8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111  :
 
                begin
 
                begin
 
                  // RST p
 
                  // RST p
 
                  MCycles = 3'b011;
 
                  MCycles = 3'b011;
 
                  case (MCycle)
 
                  case (1'b1) // MCycle
 
                    1  :
 
                    MCycle[0] :
 
                      begin
 
                      begin
 
                        TStates = 3'b101;
 
                        TStates = 3'b101;
 
                        IncDec_16 = 4'b1111;
 
                        IncDec_16 = 4'b1111;
 
                        Set_Addr_To = aSP;
 
                        Set_Addr_To = aSP;
 
                        Set_BusB_To = 4'b1101;
 
                        Set_BusB_To = 4'b1101;
 
                      end
 
                      end
 
 
 
 
 
                    2  :
 
                    MCycle[1] :
 
                      begin
 
                      begin
 
                        Write = 1'b1;
 
                        Write = 1'b1;
 
                        IncDec_16 = 4'b1111;
 
                        IncDec_16 = 4'b1111;
 
                        Set_Addr_To = aSP;
 
                        Set_Addr_To = aSP;
 
                        Set_BusB_To = 4'b1100;
 
                        Set_BusB_To = 4'b1100;
 
                      end
 
                      end
 
 
 
 
 
                    3  :
 
                    MCycle[2] :
 
                      begin
 
                      begin
 
                        Write = 1'b1;
 
                        Write = 1'b1;
 
                        RstP = 1'b1;
 
                        RstP = 1'b1;
 
                      end
 
                      end
 
 
 
 
Line 1796... Line 1766... 
                begin
 
                begin
 
                  if (Mode != 3 )
 
                  if (Mode != 3 )
 
                    begin
 
                    begin
 
                      // IN A,(n)
 
                      // IN A,(n)
 
                      MCycles = 3'b011;
 
                      MCycles = 3'b011;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            Set_Addr_To = aIOA;
 
                            Set_Addr_To = aIOA;
 
                          end
 
                          end
 
 
 
 
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            Read_To_Acc = 1'b1;
 
                            Read_To_Acc = 1'b1;
 
                            IORQ = 1'b1;
 
                            IORQ = 1'b1;
 
                          end
 
                          end
 
 
 
 
Line 1820... Line 1790... 
                begin
 
                begin
 
                  if (Mode != 3 )
 
                  if (Mode != 3 )
 
                    begin
 
                    begin
 
                      // OUT (n),A
 
                      // OUT (n),A
 
                      MCycles = 3'b011;
 
                      MCycles = 3'b011;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            Set_Addr_To = aIOA;
 
                            Set_Addr_To = aIOA;
 
                            Set_BusB_To = 4'b0111;
 
                            Set_BusB_To = 4'b0111;
 
                          end
 
                          end
 
 
 
 
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            Write = 1'b1;
 
                            Write = 1'b1;
 
                            IORQ = 1'b1;
 
                            IORQ = 1'b1;
 
                          end
 
                          end
 
 
 
 
Line 1923... Line 1893... 
                  // SRA (HL)
 
                  // SRA (HL)
 
                  // SRL (HL)
 
                  // SRL (HL)
 
                  // SLA (HL)
 
                  // SLA (HL)
 
                  // SLL (HL) (Undocumented) / SWAP (HL)
 
                  // SLL (HL) (Undocumented) / SWAP (HL)
 
                  MCycles = 3'b011;
 
                  MCycles = 3'b011;
 
                  case (MCycle)
 
                  case (1'b1) // MCycle
 
                    1 , 7  :
 
                    MCycle[0], MCycle[6] :
 
                      Set_Addr_To = aXY;
 
                      Set_Addr_To = aXY;
 
                    2  :
 
                    MCycle[1] :
 
                      begin
 
                      begin
 
                        ALU_Op = 4'b1000;
 
                        ALU_Op = 4'b1000;
 
                        Read_To_Reg = 1'b1;
 
                        Read_To_Reg = 1'b1;
 
                        Save_ALU = 1'b1;
 
                        Save_ALU = 1'b1;
 
                        Set_Addr_To = aXY;
 
                        Set_Addr_To = aXY;
 
                        TStates = 3'b100;
 
                        TStates = 3'b100;
 
                      end
 
                      end
 
 
 
 
 
                    3  :
 
                    MCycle[2] :
 
                      Write = 1'b1;
 
                      Write = 1'b1;
 
                    default :;
 
                    default :;
 
                  endcase // case(MCycle)
 
                  endcase // case(MCycle)
 
                end // case: 8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110
 
                end // case: 8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110
 
 
 
 
Line 1962... Line 1932... 
 
 
 
 
              8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110  :
 
              8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110  :
 
                begin
 
                begin
 
                  // BIT b,(HL)
 
                  // BIT b,(HL)
 
                  MCycles = 3'b010;
 
                  MCycles = 3'b010;
 
                  case (MCycle)
 
                  case (1'b1) // MCycle
 
                    1 , 7  :
 
                    MCycle[0], MCycle[6] :
 
                      Set_Addr_To = aXY;
 
                      Set_Addr_To = aXY;
 
                    2  :
 
                    MCycle[1] :
 
                      begin
 
                      begin
 
                        ALU_Op = 4'b1001;
 
                        ALU_Op = 4'b1001;
 
                        TStates = 3'b100;
 
                        TStates = 3'b100;
 
                      end
 
                      end
 
 
 
 
Line 1997... Line 1967... 
 
 
 
 
              8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110  :
 
              8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110  :
 
                begin
 
                begin
 
                  // SET b,(HL)
 
                  // SET b,(HL)
 
                  MCycles = 3'b011;
 
                  MCycles = 3'b011;
 
                  case (MCycle)
 
                  case (1'b1) // MCycle
 
                    1 , 7  :
 
                    MCycle[0], MCycle[6] :
 
                      Set_Addr_To = aXY;
 
                      Set_Addr_To = aXY;
 
                    2  :
 
                    MCycle[1] :
 
                      begin
 
                      begin
 
                        ALU_Op = 4'b1010;
 
                        ALU_Op = 4'b1010;
 
                        Read_To_Reg = 1'b1;
 
                        Read_To_Reg = 1'b1;
 
                        Save_ALU = 1'b1;
 
                        Save_ALU = 1'b1;
 
                        Set_Addr_To = aXY;
 
                        Set_Addr_To = aXY;
 
                        TStates = 3'b100;
 
                        TStates = 3'b100;
 
                      end
 
                      end
 
                    3  :
 
                    MCycle[2] :
 
                      Write = 1'b1;
 
                      Write = 1'b1;
 
                    default :;
 
                    default :;
 
                  endcase // case(MCycle)
 
                  endcase // case(MCycle)
 
                end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110
 
                end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110
 
 
 
 
Line 2036... Line 2006... 
 
 
 
 
              8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110  :
 
              8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110  :
 
                begin
 
                begin
 
                  // RES b,(HL)
 
                  // RES b,(HL)
 
                  MCycles = 3'b011;
 
                  MCycles = 3'b011;
 
                  case (MCycle)
 
                  case (1'b1) // MCycle
 
                    1 , 7  :
 
                    MCycle[0], MCycle[6] :
 
                      Set_Addr_To = aXY;
 
                      Set_Addr_To = aXY;
 
                    2  :
 
                    MCycle[1] :
 
                      begin
 
                      begin
 
                        ALU_Op = 4'b1011;
 
                        ALU_Op = 4'b1011;
 
                        Read_To_Reg = 1'b1;
 
                        Read_To_Reg = 1'b1;
 
                        Save_ALU = 1'b1;
 
                        Save_ALU = 1'b1;
 
                        Set_Addr_To = aXY;
 
                        Set_Addr_To = aXY;
 
                        TStates = 3'b100;
 
                        TStates = 3'b100;
 
                      end
 
                      end
 
 
 
 
 
                    3  :
 
                    MCycle[2] :
 
                      Write = 1'b1;
 
                      Write = 1'b1;
 
                    default :;
 
                    default :;
 
                  endcase // case(MCycle)
 
                  endcase // case(MCycle)
 
                end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110
 
                end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110
 
 
 
 
Line 2133... Line 2103... 
                  // 16 BIT LOAD GROUP
 
                  // 16 BIT LOAD GROUP
 
                  8'b01001011,8'b01011011,8'b01101011,8'b01111011  :
 
                  8'b01001011,8'b01011011,8'b01101011,8'b01111011  :
 
                    begin
 
                    begin
 
                      // LD dd,(nn)
 
                      // LD dd,(nn)
 
                      MCycles = 3'b101;
 
                      MCycles = 3'b101;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            LDZ = 1'b1;
 
                            LDZ = 1'b1;
 
                          end
 
                          end
 
 
 
 
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            Set_Addr_To = aZI;
 
                            Set_Addr_To = aZI;
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            LDW = 1'b1;
 
                            LDW = 1'b1;
 
                          end
 
                          end
 
 
 
 
 
                        4  :
 
                        MCycle[3] :
 
                          begin
 
                          begin
 
                            Read_To_Reg = 1'b1;
 
                            Read_To_Reg = 1'b1;
 
                            if (IR[5:4] == 2'b11 )
 
                            if (IR[5:4] == 2'b11 )
 
                              begin
 
                              begin
 
                                Set_BusA_To = 4'b1000;
 
                                Set_BusA_To = 4'b1000;
Line 2163... Line 2133... 
                              end
 
                              end
 
                            Inc_WZ = 1'b1;
 
                            Inc_WZ = 1'b1;
 
                            Set_Addr_To = aZI;
 
                            Set_Addr_To = aZI;
 
                          end // case: 4
 
                          end // case: 4
 
 
 
 
 
                        5  :
 
                        MCycle[4] :
 
                          begin
 
                          begin
 
                            Read_To_Reg = 1'b1;
 
                            Read_To_Reg = 1'b1;
 
                            if (IR[5:4] == 2'b11 )
 
                            if (IR[5:4] == 2'b11 )
 
                              begin
 
                              begin
 
                                Set_BusA_To = 4'b1001;
 
                                Set_BusA_To = 4'b1001;
Line 2186... Line 2156... 
 
 
 
 
                  8'b01000011,8'b01010011,8'b01100011,8'b01110011  :
 
                  8'b01000011,8'b01010011,8'b01100011,8'b01110011  :
 
                    begin
 
                    begin
 
                      // LD (nn),dd
 
                      // LD (nn),dd
 
                      MCycles = 3'b101;
 
                      MCycles = 3'b101;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            LDZ = 1'b1;
 
                            LDZ = 1'b1;
 
                          end
 
                          end
 
 
 
 
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            Set_Addr_To = aZI;
 
                            Set_Addr_To = aZI;
 
                            Inc_PC = 1'b1;
 
                            Inc_PC = 1'b1;
 
                            LDW = 1'b1;
 
                            LDW = 1'b1;
 
                            if (IR[5:4] == 2'b11 )
 
                            if (IR[5:4] == 2'b11 )
Line 2210... Line 2180... 
                                Set_BusB_To[0] = 1'b1;
 
                                Set_BusB_To[0] = 1'b1;
 
                                Set_BusB_To[3] = 1'b0;
 
                                Set_BusB_To[3] = 1'b0;
 
                              end
 
                              end
 
                          end // case: 3
 
                          end // case: 3
 
 
 
 
 
                        4  :
 
                        MCycle[3] :
 
                          begin
 
                          begin
 
                            Inc_WZ = 1'b1;
 
                            Inc_WZ = 1'b1;
 
                            Set_Addr_To = aZI;
 
                            Set_Addr_To = aZI;
 
                            Write = 1'b1;
 
                            Write = 1'b1;
 
                            if (IR[5:4] == 2'b11 )
 
                            if (IR[5:4] == 2'b11 )
Line 2227... Line 2197... 
                                Set_BusB_To[0] = 1'b0;
 
                                Set_BusB_To[0] = 1'b0;
 
                                Set_BusB_To[3] = 1'b0;
 
                                Set_BusB_To[3] = 1'b0;
 
                              end
 
                              end
 
                          end // case: 4
 
                          end // case: 4
 
 
 
 
 
                        5  :
 
                        MCycle[4] :
 
                          begin
 
                          begin
 
                            Write = 1'b1;
 
                            Write = 1'b1;
 
                          end
 
                          end
 
 
 
 
 
                        default :;
 
                        default :;
Line 2240... Line 2210... 
 
 
 
 
                  8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000  :
 
                  8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000  :
 
                    begin
 
                    begin
 
                      // LDI, LDD, LDIR, LDDR
 
                      // LDI, LDD, LDIR, LDDR
 
                      MCycles = 3'b100;
 
                      MCycles = 3'b100;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        1  :
 
                        MCycle[0] :
 
                          begin
 
                          begin
 
                            Set_Addr_To = aXY;
 
                            Set_Addr_To = aXY;
 
                            IncDec_16 = 4'b1100; // BC
 
                            IncDec_16 = 4'b1100; // BC
 
                          end
 
                          end
 
 
 
 
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Set_BusB_To = 4'b0110;
 
                            Set_BusB_To = 4'b0110;
 
                            Set_BusA_To[2:0] = 3'b111;
 
                            Set_BusA_To[2:0] = 3'b111;
 
                            ALU_Op = 4'b0000;
 
                            ALU_Op = 4'b0000;
 
                            Set_Addr_To = aDE;
 
                            Set_Addr_To = aDE;
Line 2263... Line 2233... 
                              begin
 
                              begin
 
                                IncDec_16 = 4'b1110;
 
                                IncDec_16 = 4'b1110;
 
                              end
 
                              end
 
                          end // case: 2
 
                          end // case: 2
 
 
 
 
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            I_BT = 1'b1;
 
                            I_BT = 1'b1;
 
                            TStates = 3'b101;
 
                            TStates = 3'b101;
 
                            Write = 1'b1;
 
                            Write = 1'b1;
 
                            if (IR[3] == 1'b0 )
 
                            if (IR[3] == 1'b0 )
Line 2278... Line 2248... 
                              begin
 
                              begin
 
                                IncDec_16 = 4'b1101;
 
                                IncDec_16 = 4'b1101;
 
                              end
 
                              end
 
                          end // case: 3
 
                          end // case: 3
 
 
 
 
 
                        4  :
 
                        MCycle[3] :
 
                          begin
 
                          begin
 
                            NoRead = 1'b1;
 
                            NoRead = 1'b1;
 
                            TStates = 3'b101;
 
                            TStates = 3'b101;
 
                          end
 
                          end
 
 
 
 
Line 2292... Line 2262... 
 
 
 
 
                  8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001  :
 
                  8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001  :
 
                    begin
 
                    begin
 
                      // CPI, CPD, CPIR, CPDR
 
                      // CPI, CPD, CPIR, CPDR
 
                      MCycles = 3'b100;
 
                      MCycles = 3'b100;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        1  :
 
                        MCycle[0] :
 
                          begin
 
                          begin
 
                            Set_Addr_To = aXY;
 
                            Set_Addr_To = aXY;
 
                            IncDec_16 = 4'b1100; // BC
 
                            IncDec_16 = 4'b1100; // BC
 
                          end
 
                          end
 
 
 
 
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Set_BusB_To = 4'b0110;
 
                            Set_BusB_To = 4'b0110;
 
                            Set_BusA_To[2:0] = 3'b111;
 
                            Set_BusA_To[2:0] = 3'b111;
 
                            ALU_Op = 4'b0111;
 
                            ALU_Op = 4'b0111;
 
                            Save_ALU = 1'b1;
 
                            Save_ALU = 1'b1;
Line 2316... Line 2286... 
                              begin
 
                              begin
 
                                IncDec_16 = 4'b1110;
 
                                IncDec_16 = 4'b1110;
 
                              end
 
                              end
 
                          end // case: 2
 
                          end // case: 2
 
 
 
 
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            NoRead = 1'b1;
 
                            NoRead = 1'b1;
 
                            I_BC = 1'b1;
 
                            I_BC = 1'b1;
 
                            TStates = 3'b101;
 
                            TStates = 3'b101;
 
                          end
 
                          end
 
 
 
 
 
                        4  :
 
                        MCycle[3] :
 
                          begin
 
                          begin
 
                            NoRead = 1'b1;
 
                            NoRead = 1'b1;
 
                            TStates = 3'b101;
 
                            TStates = 3'b101;
 
                          end
 
                          end
 
 
 
 
Line 2362... Line 2332... 
                  // 16 bit arithmetic
 
                  // 16 bit arithmetic
 
                  8'b01001010,8'b01011010,8'b01101010,8'b01111010  :
 
                  8'b01001010,8'b01011010,8'b01101010,8'b01111010  :
 
                    begin
 
                    begin
 
                      // ADC HL,ss
 
                      // ADC HL,ss
 
                      MCycles = 3'b011;
 
                      MCycles = 3'b011;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            NoRead = 1'b1;
 
                            NoRead = 1'b1;
 
                            ALU_Op = 4'b0001;
 
                            ALU_Op = 4'b0001;
 
                            Read_To_Reg = 1'b1;
 
                            Read_To_Reg = 1'b1;
 
                            Save_ALU = 1'b1;
 
                            Save_ALU = 1'b1;
Line 2382... Line 2352... 
                                Set_BusB_To = 4'b1000;
 
                                Set_BusB_To = 4'b1000;
 
                            endcase
 
                            endcase
 
                            TStates = 3'b100;
 
                            TStates = 3'b100;
 
                          end // case: 2
 
                          end // case: 2
 
 
 
 
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            NoRead = 1'b1;
 
                            NoRead = 1'b1;
 
                            Read_To_Reg = 1'b1;
 
                            Read_To_Reg = 1'b1;
 
                            Save_ALU = 1'b1;
 
                            Save_ALU = 1'b1;
 
                            ALU_Op = 4'b0001;
 
                            ALU_Op = 4'b0001;
Line 2408... Line 2378... 
 
 
 
 
                  8'b01000010,8'b01010010,8'b01100010,8'b01110010  :
 
                  8'b01000010,8'b01010010,8'b01100010,8'b01110010  :
 
                    begin
 
                    begin
 
                      // SBC HL,ss
 
                      // SBC HL,ss
 
                      MCycles = 3'b011;
 
                      MCycles = 3'b011;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            NoRead = 1'b1;
 
                            NoRead = 1'b1;
 
                            ALU_Op = 4'b0011;
 
                            ALU_Op = 4'b0011;
 
                            Read_To_Reg = 1'b1;
 
                            Read_To_Reg = 1'b1;
 
                            Save_ALU = 1'b1;
 
                            Save_ALU = 1'b1;
Line 2428... Line 2398... 
                                Set_BusB_To = 4'b1000;
 
                                Set_BusB_To = 4'b1000;
 
                            endcase
 
                            endcase
 
                            TStates = 3'b100;
 
                            TStates = 3'b100;
 
                          end // case: 2
 
                          end // case: 2
 
 
 
 
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            NoRead = 1'b1;
 
                            NoRead = 1'b1;
 
                            ALU_Op = 4'b0011;
 
                            ALU_Op = 4'b0011;
 
                            Read_To_Reg = 1'b1;
 
                            Read_To_Reg = 1'b1;
 
                            Save_ALU = 1'b1;
 
                            Save_ALU = 1'b1;
Line 2452... Line 2422... 
 
 
 
 
                  8'b01101111  :
 
                  8'b01101111  :
 
                    begin
 
                    begin
 
                      // RLD
 
                      // RLD
 
                      MCycles = 3'b100;
 
                      MCycles = 3'b100;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            NoRead = 1'b1;
 
                            NoRead = 1'b1;
 
                            Set_Addr_To = aXY;
 
                            Set_Addr_To = aXY;
 
                          end
 
                          end
 
 
 
 
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            Read_To_Reg = 1'b1;
 
                            Read_To_Reg = 1'b1;
 
                            Set_BusB_To[2:0] = 3'b110;
 
                            Set_BusB_To[2:0] = 3'b110;
 
                            Set_BusA_To[2:0] = 3'b111;
 
                            Set_BusA_To[2:0] = 3'b111;
 
                            ALU_Op = 4'b1101;
 
                            ALU_Op = 4'b1101;
 
                            TStates = 3'b100;
 
                            TStates = 3'b100;
 
                            Set_Addr_To = aXY;
 
                            Set_Addr_To = aXY;
 
                            Save_ALU = 1'b1;
 
                            Save_ALU = 1'b1;
 
                          end
 
                          end
 
 
 
 
 
                        4  :
 
                        MCycle[3] :
 
                          begin
 
                          begin
 
                            I_RLD = 1'b1;
 
                            I_RLD = 1'b1;
 
                            Write = 1'b1;
 
                            Write = 1'b1;
 
                          end
 
                          end
 
 
 
 
Line 2484... Line 2454... 
 
 
 
 
                  8'b01100111  :
 
                  8'b01100111  :
 
                    begin
 
                    begin
 
                      // RRD
 
                      // RRD
 
                      MCycles = 3'b100;
 
                      MCycles = 3'b100;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        2  :
 
                        MCycle[1] :
 
                          Set_Addr_To = aXY;
 
                          Set_Addr_To = aXY;
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            Read_To_Reg = 1'b1;
 
                            Read_To_Reg = 1'b1;
 
                            Set_BusB_To[2:0] = 3'b110;
 
                            Set_BusB_To[2:0] = 3'b110;
 
                            Set_BusA_To[2:0] = 3'b111;
 
                            Set_BusA_To[2:0] = 3'b111;
 
                            ALU_Op = 4'b1110;
 
                            ALU_Op = 4'b1110;
 
                            TStates = 3'b100;
 
                            TStates = 3'b100;
 
                            Set_Addr_To = aXY;
 
                            Set_Addr_To = aXY;
 
                            Save_ALU = 1'b1;
 
                            Save_ALU = 1'b1;
 
                          end
 
                          end
 
 
 
 
 
                        4  :
 
                        MCycle[3] :
 
                          begin
 
                          begin
 
                            I_RRD = 1'b1;
 
                            I_RRD = 1'b1;
 
                            Write = 1'b1;
 
                            Write = 1'b1;
 
                          end
 
                          end
 
 
 
 
Line 2512... Line 2482... 
 
 
 
 
                  8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101  :
 
                  8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101  :
 
                    begin
 
                    begin
 
                      // RETI, RETN
 
                      // RETI, RETN
 
                      MCycles = 3'b011;
 
                      MCycles = 3'b011;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        1  :
 
                        MCycle[0] :
 
                          Set_Addr_To = aSP;
 
                          Set_Addr_To = aSP;
 
 
 
 
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            IncDec_16 = 4'b0111;
 
                            IncDec_16 = 4'b0111;
 
                            Set_Addr_To = aSP;
 
                            Set_Addr_To = aSP;
 
                            LDZ = 1'b1;
 
                            LDZ = 1'b1;
 
                          end
 
                          end
 
 
 
 
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            Jump = 1'b1;
 
                            Jump = 1'b1;
 
                            IncDec_16 = 4'b0111;
 
                            IncDec_16 = 4'b0111;
 
                            I_RETN = 1'b1;
 
                            I_RETN = 1'b1;
 
                          end
 
                          end
Line 2538... Line 2508... 
 
 
 
 
                  8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000  :
 
                  8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000  :
 
                    begin
 
                    begin
 
                      // IN r,(C)
 
                      // IN r,(C)
 
                      MCycles = 3'b010;
 
                      MCycles = 3'b010;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        1  :
 
                        MCycle[0] :
 
                          Set_Addr_To = aBC;
 
                          Set_Addr_To = aBC;
 
 
 
 
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            IORQ = 1'b1;
 
                            IORQ = 1'b1;
 
                            if (IR[5:3] != 3'b110 )
 
                            if (IR[5:3] != 3'b110 )
 
                              begin
 
                              begin
 
                                Read_To_Reg = 1'b1;
 
                                Read_To_Reg = 1'b1;
Line 2562... Line 2532... 
                  8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001  :
 
                  8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001  :
 
                    begin
 
                    begin
 
                      // OUT (C),r
 
                      // OUT (C),r
 
                      // OUT (C),0
 
                      // OUT (C),0
 
                      MCycles = 3'b010;
 
                      MCycles = 3'b010;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        1  :
 
                        MCycle[0] :
 
                          begin
 
                          begin
 
                            Set_Addr_To = aBC;
 
                            Set_Addr_To = aBC;
 
                            Set_BusB_To[2:0]     = IR[5:3];
 
                            Set_BusB_To[2:0]     = IR[5:3];
 
                            if (IR[5:3] == 3'b110 )
 
                            if (IR[5:3] == 3'b110 )
 
                              begin
 
                              begin
 
                                Set_BusB_To[3] = 1'b1;
 
                                Set_BusB_To[3] = 1'b1;
 
                              end
 
                              end
 
                          end
 
                          end
 
 
 
 
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Write = 1'b1;
 
                            Write = 1'b1;
 
                            IORQ = 1'b1;
 
                            IORQ = 1'b1;
 
                          end
 
                          end
 
 
 
 
Line 2587... Line 2557... 
 
 
 
 
                  8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010  :
 
                  8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010  :
 
                    begin
 
                    begin
 
                      // INI, IND, INIR, INDR
 
                      // INI, IND, INIR, INDR
 
                      MCycles = 3'b100;
 
                      MCycles = 3'b100;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        1  :
 
                        MCycle[0] :
 
                          begin
 
                          begin
 
                            Set_Addr_To = aBC;
 
                            Set_Addr_To = aBC;
 
                            Set_BusB_To = 4'b1010;
 
                            Set_BusB_To = 4'b1010;
 
                            Set_BusA_To = 4'b0000;
 
                            Set_BusA_To = 4'b0000;
 
                            Read_To_Reg = 1'b1;
 
                            Read_To_Reg = 1'b1;
 
                            Save_ALU = 1'b1;
 
                            Save_ALU = 1'b1;
 
                            ALU_Op = 4'b0010;
 
                            ALU_Op = 4'b0010;
 
                          end
 
                          end
 
 
 
 
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            IORQ = 1'b1;
 
                            IORQ = 1'b1;
 
                            Set_BusB_To = 4'b0110;
 
                            Set_BusB_To = 4'b0110;
 
                            Set_Addr_To = aXY;
 
                            Set_Addr_To = aXY;
 
                          end
 
                          end
 
 
 
 
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            if (IR[3] == 1'b0 )
 
                            if (IR[3] == 1'b0 )
 
                              begin
 
                              begin
 
                                IncDec_16 = 4'b0010;
 
                                IncDec_16 = 4'b0010;
 
                              end
 
                              end
Line 2620... Line 2590... 
                            TStates = 3'b100;
 
                            TStates = 3'b100;
 
                            Write = 1'b1;
 
                            Write = 1'b1;
 
                            I_BTR = 1'b1;
 
                            I_BTR = 1'b1;
 
                          end // case: 3
 
                          end // case: 3
 
 
 
 
 
                        4  :
 
                        MCycle[3] :
 
                          begin
 
                          begin
 
                            NoRead = 1'b1;
 
                            NoRead = 1'b1;
 
                            TStates = 3'b101;
 
                            TStates = 3'b101;
 
                          end
 
                          end
 
 
 
 
Line 2634... Line 2604... 
 
 
 
 
                  8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011  :
 
                  8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011  :
 
                    begin
 
                    begin
 
                      // OUTI, OUTD, OTIR, OTDR
 
                      // OUTI, OUTD, OTIR, OTDR
 
                      MCycles = 3'b100;
 
                      MCycles = 3'b100;
 
                      case (MCycle)
 
                      case (1'b1) // MCycle
 
                        1  :
 
                        MCycle[0] :
 
                          begin
 
                          begin
 
                            TStates = 3'b101;
 
                            TStates = 3'b101;
 
                            Set_Addr_To = aXY;
 
                            Set_Addr_To = aXY;
 
                            Set_BusB_To = 4'b1010;
 
                            Set_BusB_To = 4'b1010;
 
                            Set_BusA_To = 4'b0000;
 
                            Set_BusA_To = 4'b0000;
 
                            Read_To_Reg = 1'b1;
 
                            Read_To_Reg = 1'b1;
 
                            Save_ALU = 1'b1;
 
                            Save_ALU = 1'b1;
 
                            ALU_Op = 4'b0010;
 
                            ALU_Op = 4'b0010;
 
                          end
 
                          end
 
 
 
 
 
                        2  :
 
                        MCycle[1] :
 
                          begin
 
                          begin
 
                            Set_BusB_To = 4'b0110;
 
                            Set_BusB_To = 4'b0110;
 
                            Set_Addr_To = aBC;
 
                            Set_Addr_To = aBC;
 
                          end
 
                          end
 
 
 
 
 
                        3  :
 
                        MCycle[2] :
 
                          begin
 
                          begin
 
                            if (IR[3] == 1'b0 )
 
                            if (IR[3] == 1'b0 )
 
                              begin
 
                              begin
 
                                IncDec_16 = 4'b0010;
 
                                IncDec_16 = 4'b0010;
 
                              end
 
                              end
Line 2667... Line 2637... 
                            IORQ = 1'b1;
 
                            IORQ = 1'b1;
 
                            Write = 1'b1;
 
                            Write = 1'b1;
 
                            I_BTR = 1'b1;
 
                            I_BTR = 1'b1;
 
                          end // case: 3
 
                          end // case: 3
 
 
 
 
 
                        4  :
 
                        MCycle[3] :
 
                          begin
 
                          begin
 
                            NoRead = 1'b1;
 
                            NoRead = 1'b1;
 
                            TStates = 3'b101;
 
                            TStates = 3'b101;
 
                          end
 
                          end
 
 
 
 
Line 2749... Line 2719... 
        end // if (Mode < 2 )      
        end // if (Mode < 2 )      
 
 
 
 
    end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)
 
    end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)
 
 
 
 
 
// synopsys dc_script_begin
 
// synopsys dc_script_begin
 
// set_attribute current_design "revision" "$Id: tv80_mcode.v,v 1.2 2004-09-21 17:32:52 ghutchis Exp $" -type string -quiet
 
// set_attribute current_design "revision" "$Id: tv80_mcode.v,v 1.3 2004-09-22 18:07:14 ghutchis Exp $" -type string -quiet
 
// synopsys dc_script_end
 
// synopsys dc_script_end
 
endmodule // T80_MCode
 
endmodule // T80_MCode
 
 
 
 
 
 
 
 
 
 
 
 

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