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https://opencores.org/ocsvn/tv80/tv80/trunk
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| Rev 2 |
Rev 21 |
| Line 61... |
Line 61... |
wire intcycle_n;
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wire intcycle_n;
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wire no_read;
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wire no_read;
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wire write;
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wire write;
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wire iorq;
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wire iorq;
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reg [7:0] di_reg;
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reg [7:0] di_reg;
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wire [2:0] mcycle;
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wire [6:0] mcycle;
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wire [2:0] tstate;
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wire [6:0] tstate;
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assign cen = 1;
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assign cen = 1;
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tv80_core i_tv80_core
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tv80_core i_tv80_core
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(
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(
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| Line 109... |
Line 109... |
begin
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begin
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rd_n <= #1 1'b1;
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rd_n <= #1 1'b1;
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wr_n <= #1 1'b1;
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wr_n <= #1 1'b1;
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iorq_n <= #1 1'b1;
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iorq_n <= #1 1'b1;
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mreq_n <= #1 1'b1;
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mreq_n <= #1 1'b1;
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if (mcycle == 3'b001)
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if (mcycle[0])
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begin
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begin
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if (tstate == 3'b001 || (tstate == 3'b010 && wait_n == 1'b0))
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if (tstate[1] || (tstate[2] && wait_n == 1'b0))
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begin
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begin
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rd_n <= #1 ~ intcycle_n;
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rd_n <= #1 ~ intcycle_n;
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mreq_n <= #1 ~ intcycle_n;
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mreq_n <= #1 ~ intcycle_n;
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iorq_n <= #1 intcycle_n;
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iorq_n <= #1 intcycle_n;
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end
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end
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if (tstate == 3'b011)
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if (tstate[3])
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mreq_n <= #1 1'b0;
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mreq_n <= #1 1'b0;
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end // if (mcycle == 3'b001)
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end // if (mcycle[0])
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else
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else
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begin
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begin
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if ((tstate == 3'b001 || (tstate == 3'b010 && wait_n == 1'b0)) && no_read == 1'b0 && write == 1'b0)
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if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && no_read == 1'b0 && write == 1'b0)
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begin
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begin
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rd_n <= #1 1'b0;
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rd_n <= #1 1'b0;
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iorq_n <= #1 ~ iorq;
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iorq_n <= #1 ~ iorq;
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mreq_n <= #1 iorq;
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mreq_n <= #1 iorq;
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end
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end
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if (T2Write == 0)
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if (T2Write == 0)
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begin
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begin
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if (tstate == 3'b010 && write == 1'b1)
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if (tstate[2] && write == 1'b1)
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begin
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begin
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wr_n <= #1 1'b0;
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wr_n <= #1 1'b0;
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iorq_n <= #1 ~ iorq;
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iorq_n <= #1 ~ iorq;
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mreq_n <= #1 iorq;
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mreq_n <= #1 iorq;
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end
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end
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end
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end
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else
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else
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begin
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begin
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if ((tstate == 3'b001 || (tstate == 3'b010 && wait_n == 1'b0)) && write == 1'b1)
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if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && write == 1'b1)
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begin
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begin
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wr_n <= #1 1'b0;
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wr_n <= #1 1'b0;
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iorq_n <= #1 ~ iorq;
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iorq_n <= #1 ~ iorq;
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mreq_n <= #1 iorq;
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mreq_n <= #1 iorq;
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end
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end
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end // else: !if(T2write == 0)
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end // else: !if(T2write == 0)
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end // else: !if(mcycle == 3'b001)
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end // else: !if(mcycle[0])
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if (tstate == 3'b010 && wait_n == 1'b1)
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if (tstate[2] && wait_n == 1'b1)
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di_reg <= #1 di;
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di_reg <= #1 di;
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end // else: !if(!reset_n)
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end // else: !if(!reset_n)
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end // always @ (posedge clk or negedge reset_n)
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end // always @ (posedge clk or negedge reset_n)
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endmodule // t80s
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endmodule // t80s
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