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[/] [tv80/] [branches/] [restruc2/] [rtl/] [core/] [tv80_reg.v] - Diff between revs 47 and 48

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Rev 47 Rev 48
Line 61... Line 61...
  assign DOCL = RegsL[AddrC];
  assign DOCL = RegsL[AddrC];
 
 
  // break out ram bits for waveform debug
  // break out ram bits for waveform debug
  wire [7:0] H = RegsH[2];
  wire [7:0] H = RegsH[2];
  wire [7:0] L = RegsL[2];
  wire [7:0] L = RegsL[2];
 
  wire [7:0] B = RegsH[0];
 
  wire [7:0] C = RegsL[0];
 
  wire [7:0] D = RegsH[1];
 
  wire [7:0] E = RegsL[1];
 
 
// synopsys dc_script_begin
// synopsys dc_script_begin
// set_attribute current_design "revision" "$Id: tv80_reg.v,v 1.1 2004-05-16 17:39:57 ghutchis Exp $" -type string -quiet
// set_attribute current_design "revision" "$Id: tv80_reg.v,v 1.1.8.1 2004-11-30 21:58:10 ghutchis Exp $" -type string -quiet
// synopsys dc_script_end
// synopsys dc_script_end
endmodule
endmodule
 
 
 
 
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