| Line 206... |
Line 206... |
SSS = IR[2:0];
|
SSS = IR[2:0];
|
DPAIR = IR[5:4];
|
DPAIR = IR[5:4];
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IRB = IR;
|
IRB = IR;
|
|
|
MCycles = 3'b001;
|
MCycles = 3'b001;
|
if (MCycle == 3'b001 )
|
if (MCycle[0] )
|
begin
|
begin
|
TStates = 3'b100;
|
TStates = 3'b100;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
| Line 928... |
Line 928... |
// AND A,n
|
// AND A,n
|
// OR A,n
|
// OR A,n
|
// XOR A,n
|
// XOR A,n
|
// CP A,n
|
// CP A,n
|
MCycles = 3'b010;
|
MCycles = 3'b010;
|
if (MCycle == 3'b010 )
|
if (MCycle[1] )
|
begin
|
begin
|
Inc_PC = 1'b1;
|
Inc_PC = 1'b1;
|
Read_To_Reg = 1'b1;
|
Read_To_Reg = 1'b1;
|
Save_ALU = 1'b1;
|
Save_ALU = 1'b1;
|
Set_BusB_To[2:0] = SSS;
|
Set_BusB_To[2:0] = SSS;
|
| Line 1905... |
Line 1905... |
// RR r
|
// RR r
|
// SLA r
|
// SLA r
|
// SRA r
|
// SRA r
|
// SRL r
|
// SRL r
|
// SLL r (Undocumented) / SWAP r
|
// SLL r (Undocumented) / SWAP r
|
if (MCycle == 3'b001 ) begin
|
if (MCycle[0] ) begin
|
ALU_Op = 4'b1000;
|
ALU_Op = 4'b1000;
|
Read_To_Reg = 1'b1;
|
Read_To_Reg = 1'b1;
|
Save_ALU = 1'b1;
|
Save_ALU = 1'b1;
|
end
|
end
|
end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,...
|
end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,...
|
| Line 1951... |
Line 1951... |
8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111,
|
8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111,
|
8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111,
|
8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111,
|
8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 :
|
8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 :
|
begin
|
begin
|
// BIT b,r
|
// BIT b,r
|
if (MCycle == 3'b001 )
|
if (MCycle[0] )
|
begin
|
begin
|
Set_BusB_To[2:0] = IR[2:0];
|
Set_BusB_To[2:0] = IR[2:0];
|
ALU_Op = 4'b1001;
|
ALU_Op = 4'b1001;
|
end
|
end
|
end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,...
|
end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,...
|
| Line 1985... |
Line 1985... |
8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101111,
|
8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101111,
|
8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110111,
|
8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110111,
|
8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111111 :
|
8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111111 :
|
begin
|
begin
|
// SET b,r
|
// SET b,r
|
if (MCycle == 3'b001 )
|
if (MCycle[0] )
|
begin
|
begin
|
ALU_Op = 4'b1010;
|
ALU_Op = 4'b1010;
|
Read_To_Reg = 1'b1;
|
Read_To_Reg = 1'b1;
|
Save_ALU = 1'b1;
|
Save_ALU = 1'b1;
|
end
|
end
|
| Line 2024... |
Line 2024... |
8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111,
|
8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111,
|
8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111,
|
8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111,
|
8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 :
|
8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 :
|
begin
|
begin
|
// RES b,r
|
// RES b,r
|
if (MCycle == 3'b001 )
|
if (MCycle[0] )
|
begin
|
begin
|
ALU_Op = 4'b1011;
|
ALU_Op = 4'b1011;
|
Read_To_Reg = 1'b1;
|
Read_To_Reg = 1'b1;
|
Save_ALU = 1'b1;
|
Save_ALU = 1'b1;
|
end
|
end
|
| Line 2683... |
Line 2683... |
end // block: default_ed_block
|
end // block: default_ed_block
|
endcase // case(ISet)
|
endcase // case(ISet)
|
|
|
if (Mode == 1 )
|
if (Mode == 1 )
|
begin
|
begin
|
if (MCycle == 3'b001 )
|
if (MCycle[0] )
|
begin
|
begin
|
//TStates = 3'b100;
|
//TStates = 3'b100;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
| Line 2695... |
Line 2695... |
end
|
end
|
end
|
end
|
|
|
if (Mode == 3 )
|
if (Mode == 3 )
|
begin
|
begin
|
if (MCycle == 3'b001 )
|
if (MCycle[0] )
|
begin
|
begin
|
//TStates = 3'b100;
|
//TStates = 3'b100;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
| Line 2707... |
Line 2707... |
end
|
end
|
end
|
end
|
|
|
if (Mode < 2 )
|
if (Mode < 2 )
|
begin
|
begin
|
if (MCycle == 3'b110 )
|
if (MCycle[5] )
|
begin
|
begin
|
Inc_PC = 1'b1;
|
Inc_PC = 1'b1;
|
if (Mode == 1 )
|
if (Mode == 1 )
|
begin
|
begin
|
Set_Addr_To = aXY;
|
Set_Addr_To = aXY;
|
| Line 2722... |
Line 2722... |
if (IRB == 8'b00110110 || IRB == 8'b11001011 )
|
if (IRB == 8'b00110110 || IRB == 8'b11001011 )
|
begin
|
begin
|
Set_Addr_To = aNone;
|
Set_Addr_To = aNone;
|
end
|
end
|
end
|
end
|
if (MCycle == 3'b111 )
|
if (MCycle[6] )
|
begin
|
begin
|
if (Mode == 0 )
|
if (Mode == 0 )
|
begin
|
begin
|
TStates = 3'b101;
|
TStates = 3'b101;
|
end
|
end
|
| Line 2749... |
Line 2749... |
end // if (Mode < 2 )
|
end // if (Mode < 2 )
|
|
|
end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)
|
end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)
|
|
|
// synopsys dc_script_begin
|
// synopsys dc_script_begin
|
// set_attribute current_design "revision" "$Id: tv80_mcode.v,v 1.1 2004-05-16 17:39:57 ghutchis Exp $" -type string -quiet
|
// set_attribute current_design "revision" "$Id: tv80_mcode.v,v 1.2 2004-09-21 17:32:52 ghutchis Exp $" -type string -quiet
|
// synopsys dc_script_end
|
// synopsys dc_script_end
|
endmodule // T80_MCode
|
endmodule // T80_MCode
|
|
|
|
|
|
|
