| Line 20... |
Line 20... |
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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module tv80_mcode (/*AUTOARG*/
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module tv80_mcode
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(/*AUTOARG*/
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// Outputs
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// Outputs
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MCycles, TStates, Prefix, Inc_PC, Inc_WZ, IncDec_16, Read_To_Reg,
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MCycles, TStates, Prefix, Inc_PC, Inc_WZ, IncDec_16, Read_To_Reg,
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Read_To_Acc, Set_BusA_To, Set_BusB_To, ALU_Op, Save_ALU, PreserveC,
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Read_To_Acc, Set_BusA_To, Set_BusB_To, ALU_Op, Save_ALU, PreserveC,
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Arith16, Set_Addr_To, IORQ, Jump, JumpE, JumpXY, Call, RstP, LDZ,
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Arith16, Set_Addr_To, IORQ, Jump, JumpE, JumpXY, Call, RstP, LDZ,
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LDW, LDSPHL, Special_LD, ExchangeDH, ExchangeRp, ExchangeAF,
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LDW, LDSPHL, Special_LD, ExchangeDH, ExchangeRp, ExchangeAF,
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| Line 269... |
Line 270... |
//
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//
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// Unprefixed instructions
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// Unprefixed instructions
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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case (IRB)
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casex (IRB)
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// 8 BIT LOAD GROUP
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// 8 BIT LOAD GROUP
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8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,
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8'b01xxxxxx :
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8'b01001000,8'b01001001,8'b01001010,8'b01001011,8'b01001100,8'b01001101,8'b01001111,
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8'b01010000,8'b01010001,8'b01010010,8'b01010011,8'b01010100,8'b01010101,8'b01010111,
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8'b01011000,8'b01011001,8'b01011010,8'b01011011,8'b01011100,8'b01011101,8'b01011111,
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8'b01100000,8'b01100001,8'b01100010,8'b01100011,8'b01100100,8'b01100101,8'b01100111,
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8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111,
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8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 :
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begin
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// LD r,r'
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Set_BusB_To[2:0] = SSS;
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ExchangeRp = 1'b1;
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Set_BusA_To[2:0] = DDD;
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Read_To_Reg = 1'b1;
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end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,...
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8'b00000110,8'b00001110,8'b00010110,8'b00011110,8'b00100110,8'b00101110,8'b00111110 :
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begin
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begin
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// LD r,n
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if (IRB[5:0] == 6'b110110)
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MCycles = 3'b010;
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Halt = 1'b1;
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if (MCycle[1])
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else if (IRB[2:0] == 3'b110)
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begin
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Inc_PC = 1'b1;
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Set_BusA_To[2:0] = DDD;
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Read_To_Reg = 1'b1;
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end
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end // case: 8'b00000110,8'b00001110,8'b00010110,8'b00011110,8'b00100110,8'b00101110,8'b00111110
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8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01111110 :
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begin
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begin
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// LD r,(HL)
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// LD r,(HL)
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MCycles = 3'b010;
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MCycles = 3'b010;
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if (MCycle[0])
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if (MCycle[0])
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Set_Addr_To = aXY;
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Set_Addr_To = aXY;
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if (MCycle[1])
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if (MCycle[1])
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begin
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begin
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Set_BusA_To[2:0] = DDD;
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Set_BusA_To[2:0] = DDD;
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Read_To_Reg = 1'b1;
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Read_To_Reg = 1'b1;
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end
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end
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end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01111110
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end // if (IRB[2:0] == 3'b110)
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else if (IRB[5:3] == 3'b110)
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8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111 :
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begin
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begin
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// LD (HL),r
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// LD (HL),r
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MCycles = 3'b010;
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MCycles = 3'b010;
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if (MCycle[0])
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if (MCycle[0])
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begin
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begin
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| Line 324... |
Line 300... |
Set_BusB_To[2:0] = SSS;
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Set_BusB_To[2:0] = SSS;
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Set_BusB_To[3] = 1'b0;
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Set_BusB_To[3] = 1'b0;
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end
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end
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if (MCycle[1])
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if (MCycle[1])
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Write = 1'b1;
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Write = 1'b1;
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end // case: 8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111
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end // if (IRB[5:3] == 3'b110)
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else
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begin
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Set_BusB_To[2:0] = SSS;
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ExchangeRp = 1'b1;
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Set_BusA_To[2:0] = DDD;
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Read_To_Reg = 1'b1;
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end // else: !if(IRB[5:3] == 3'b110)
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end // case: 8'b01xxxxxx
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8'b00110110 :
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8'b00xxx110 :
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begin
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if (IRB[5:3] == 3'b110)
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begin
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begin
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// LD (HL),n
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// LD (HL),n
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MCycles = 3'b011;
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MCycles = 3'b011;
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if (MCycle[1])
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if (MCycle[1])
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begin
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begin
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| Line 339... |
Line 325... |
Set_BusB_To[2:0] = SSS;
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Set_BusB_To[2:0] = SSS;
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Set_BusB_To[3] = 1'b0;
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Set_BusB_To[3] = 1'b0;
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end
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end
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if (MCycle[2])
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if (MCycle[2])
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Write = 1'b1;
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Write = 1'b1;
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end // case: 8'b00110110
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end // if (IRB[5:3] == 3'b110)
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else
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begin
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// LD r,n
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MCycles = 3'b010;
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if (MCycle[1])
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begin
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Inc_PC = 1'b1;
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Set_BusA_To[2:0] = DDD;
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Read_To_Reg = 1'b1;
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end
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end
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end
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8'b00001010 :
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8'b00001010 :
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begin
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begin
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// LD A,(BC)
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// LD A,(BC)
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MCycles = 3'b010;
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MCycles = 3'b010;
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| Line 625... |
Line 623... |
// LD SP,HL
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// LD SP,HL
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TStates = 3'b110;
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TStates = 3'b110;
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LDSPHL = 1'b1;
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LDSPHL = 1'b1;
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end
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end
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8'b11000101,8'b11010101,8'b11100101,8'b11110101 :
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8'b11xx0101 :
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begin
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begin
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// PUSH qq
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// PUSH qq
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MCycles = 3'b011;
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MCycles = 3'b011;
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case (1'b1) // MCycle
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case (1'b1) // MCycle
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MCycle[0] :
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MCycle[0] :
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| Line 670... |
Line 668... |
Write = 1'b1;
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Write = 1'b1;
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default :;
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default :;
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endcase // case(MCycle)
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endcase // case(MCycle)
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end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101
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end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101
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8'b11000001,8'b11010001,8'b11100001,8'b11110001 :
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8'b11xx0001 :
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begin
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begin
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// POP qq
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// POP qq
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MCycles = 3'b011;
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MCycles = 3'b011;
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case (1'b1) // MCycle
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case (1'b1) // MCycle
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MCycle[0] :
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MCycle[0] :
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| Line 841... |
Line 839... |
end // if (Mode != 3 )
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end // if (Mode != 3 )
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end // case: 8'b11100011
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end // case: 8'b11100011
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// 8 BIT ARITHMETIC AND LOGICAL GROUP
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// 8 BIT ARITHMETIC AND LOGICAL GROUP
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8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,
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8'b10xxxxxx :
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8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001111,
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8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010111,
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8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011111,
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8'b10100000,8'b10100001,8'b10100010,8'b10100011,8'b10100100,8'b10100101,8'b10100111,
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8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111,
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8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111,
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8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 :
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begin
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begin
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// ADD A,r
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if (IR[2:0] == 3'b110)
|
// ADC A,r
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// SUB A,r
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// SBC A,r
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// AND A,r
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// OR A,r
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// XOR A,r
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|
// CP A,r
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Set_BusB_To[2:0] = SSS;
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Set_BusA_To[2:0] = 3'b111;
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Read_To_Reg = 1'b1;
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Save_ALU = 1'b1;
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end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
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8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 :
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begin
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begin
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// ADD A,(HL)
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// ADD A,(HL)
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// ADC A,(HL)
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// ADC A,(HL)
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// SUB A,(HL)
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// SUB A,(HL)
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// SBC A,(HL)
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// SBC A,(HL)
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| Line 888... |
Line 865... |
Set_BusA_To[2:0] = 3'b111;
|
Set_BusA_To[2:0] = 3'b111;
|
end
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end
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default :;
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default :;
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endcase // case(MCycle)
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endcase // case(MCycle)
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end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110
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end // if (IR[2:0] == 3'b110)
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else
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begin
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|
// ADD A,r
|
|
// ADC A,r
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|
// SUB A,r
|
|
// SBC A,r
|
|
// AND A,r
|
|
// OR A,r
|
|
// XOR A,r
|
|
// CP A,r
|
|
Set_BusB_To[2:0] = SSS;
|
|
Set_BusA_To[2:0] = 3'b111;
|
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Read_To_Reg = 1'b1;
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Save_ALU = 1'b1;
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end // else: !if(IR[2:0] == 3'b110)
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end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
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|
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8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 :
|
8'b11xxx110 :
|
begin
|
begin
|
// ADD A,n
|
// ADD A,n
|
// ADC A,n
|
// ADC A,n
|
// SUB A,n
|
// SUB A,n
|
// SBC A,n
|
// SBC A,n
|
| Line 909... |
Line 902... |
Read_To_Reg = 1'b1;
|
Read_To_Reg = 1'b1;
|
Save_ALU = 1'b1;
|
Save_ALU = 1'b1;
|
Set_BusB_To[2:0] = SSS;
|
Set_BusB_To[2:0] = SSS;
|
Set_BusA_To[2:0] = 3'b111;
|
Set_BusA_To[2:0] = 3'b111;
|
end
|
end
|
end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110
|
|
|
|
8'b00000100,8'b00001100,8'b00010100,8'b00011100,8'b00100100,8'b00101100,8'b00111100 :
|
|
begin
|
|
// INC r
|
|
Set_BusB_To = 4'b1010;
|
|
Set_BusA_To[2:0] = DDD;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
PreserveC = 1'b1;
|
|
ALU_Op = 4'b0000;
|
|
end
|
end
|
|
|
8'b00110100 :
|
8'b00xxx100 :
|
|
begin
|
|
if (IRB[5:3] == 3'b110)
|
begin
|
begin
|
// INC (HL)
|
// INC (HL)
|
MCycles = 3'b011;
|
MCycles = 3'b011;
|
case (1'b1) // MCycle
|
case (1'b1) // MCycle
|
MCycle[0] :
|
MCycle[0] :
|
| Line 946... |
Line 930... |
MCycle[2] :
|
MCycle[2] :
|
Write = 1'b1;
|
Write = 1'b1;
|
default :;
|
default :;
|
endcase // case(MCycle)
|
endcase // case(MCycle)
|
end // case: 8'b00110100
|
end // case: 8'b00110100
|
|
else
|
8'b00000101,8'b00001101,8'b00010101,8'b00011101,8'b00100101,8'b00101101,8'b00111101 :
|
|
begin
|
begin
|
// DEC r
|
// INC r
|
Set_BusB_To = 4'b1010;
|
Set_BusB_To = 4'b1010;
|
Set_BusA_To[2:0] = DDD;
|
Set_BusA_To[2:0] = DDD;
|
Read_To_Reg = 1'b1;
|
Read_To_Reg = 1'b1;
|
Save_ALU = 1'b1;
|
Save_ALU = 1'b1;
|
PreserveC = 1'b1;
|
PreserveC = 1'b1;
|
ALU_Op = 4'b0010;
|
ALU_Op = 4'b0000;
|
|
end
|
end
|
end
|
|
|
8'b00110101 :
|
8'b00xxx101 :
|
|
begin
|
|
if (IRB[5:3] == 3'b110)
|
begin
|
begin
|
// DEC (HL)
|
// DEC (HL)
|
MCycles = 3'b011;
|
MCycles = 3'b011;
|
case (1'b1) // MCycle
|
case (1'b1) // MCycle
|
MCycle[0] :
|
MCycle[0] :
|
| Line 981... |
Line 967... |
|
|
MCycle[2] :
|
MCycle[2] :
|
Write = 1'b1;
|
Write = 1'b1;
|
default :;
|
default :;
|
endcase // case(MCycle)
|
endcase // case(MCycle)
|
end // case: 8'b00110101
|
end
|
|
else
|
|
begin
|
|
// DEC r
|
|
Set_BusB_To = 4'b1010;
|
|
Set_BusA_To[2:0] = DDD;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
PreserveC = 1'b1;
|
|
ALU_Op = 4'b0010;
|
|
end
|
|
end
|
|
|
// GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
|
// GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
|
8'b00100111 :
|
8'b00100111 :
|
begin
|
begin
|
// DAA
|
// DAA
|
| Line 1081... |
Line 1078... |
default :;
|
default :;
|
endcase
|
endcase
|
end
|
end
|
end // case: 8'b00000000
|
end // case: 8'b00000000
|
|
|
8'b01110110 :
|
|
// HALT
|
|
Halt = 1'b1;
|
|
|
|
8'b11110011 :
|
8'b11110011 :
|
// DI
|
// DI
|
SetDI = 1'b1;
|
SetDI = 1'b1;
|
|
|
8'b11111011 :
|
8'b11111011 :
|
| Line 2579... |
Line 2572... |
|
|
MCycle[2] :
|
MCycle[2] :
|
begin
|
begin
|
if (IR[3] == 1'b0 )
|
if (IR[3] == 1'b0 )
|
begin
|
begin
|
IncDec_16 = 4'b0010;
|
IncDec_16 = 4'b0110;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
IncDec_16 = 4'b1010;
|
IncDec_16 = 4'b1110;
|
end
|
end
|
TStates = 3'b100;
|
TStates = 3'b100;
|
Write = 1'b1;
|
Write = 1'b1;
|
I_BTR = 1'b1;
|
I_BTR = 1'b1;
|
end // case: 3
|
end // case: 3
|
| Line 2626... |
Line 2619... |
|
|
MCycle[2] :
|
MCycle[2] :
|
begin
|
begin
|
if (IR[3] == 1'b0 )
|
if (IR[3] == 1'b0 )
|
begin
|
begin
|
IncDec_16 = 4'b0010;
|
IncDec_16 = 4'b0110;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
IncDec_16 = 4'b1010;
|
IncDec_16 = 4'b1110;
|
end
|
end
|
IORQ = 1'b1;
|
IORQ = 1'b1;
|
Write = 1'b1;
|
Write = 1'b1;
|
I_BTR = 1'b1;
|
I_BTR = 1'b1;
|
end // case: 3
|
end // case: 3
|
| Line 2719... |
Line 2712... |
end // if (Mode < 2 )
|
end // if (Mode < 2 )
|
|
|
end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)
|
end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)
|
|
|
// synopsys dc_script_begin
|
// synopsys dc_script_begin
|
// set_attribute current_design "revision" "$Id: tv80_mcode.v,v 1.3 2004-09-22 18:07:14 ghutchis Exp $" -type string -quiet
|
// set_attribute current_design "revision" "$Id: tv80_mcode.v,v 1.4 2004-10-05 08:09:43 ghutchis Exp $" -type string -quiet
|
// synopsys dc_script_end
|
// synopsys dc_script_end
|
endmodule // T80_MCode
|
endmodule // T80_MCode
|
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No newline at end of file
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No newline at end of file
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