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<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
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<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
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<table summary="layout" width="66%" border="0" cellpadding="0" cellspacing="0"><tr><td><table summary="layout" width="100%" border="0" cellpadding="2" cellspacing="1">
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<table summary="layout" width="66%" border="0" cellpadding="0" cellspacing="0"><tr><td><table summary="layout" width="100%" border="0" cellpadding="2" cellspacing="1">
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<tr><td class="header">$Revision: 1.1 $</td><td class="header">G. Hutchison</td></tr>
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<tr><td class="header">$Revision: 1.2 $</td><td class="header">G. Hutchison</td></tr>
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<tr><td class="header"> </td><td class="header">OpenCores.org</td></tr>
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<tr><td class="header"> </td><td class="header">OpenCores.org</td></tr>
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<tr><td class="header"> </td><td class="header">October 15, 2004</td></tr>
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<tr><td class="header"> </td><td class="header">October 2004</td></tr>
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</table></td></tr></table>
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</table></td></tr></table>
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<div align="right"><span class="title"><br />tv80 Core Documentation</span></div>
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<div align="right"><span class="title"><br />tv80 Core Documentation</span></div>
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<h3>Abstract</h3>
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<h3>Abstract</h3>
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Timeout control (0x82)<br />
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Timeout control (0x82)<br />
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<a href="#anchor8">2.2.4</a>
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<a href="#anchor8">2.2.4</a>
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Max timeout (0x84, 0x83)<br />
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Max timeout (0x84, 0x83)<br />
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<a href="#anchor9">2.2.5</a>
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<a href="#anchor9">2.2.5</a>
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Interrupt countdown (0x90)<br />
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Interrupt countdown (0x90)<br />
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<a href="#anchor10">2.3</a>
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<a href="#anchor10">2.2.6</a>
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Checksum value (0x91)<br />
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<a href="#anchor11">2.2.7</a>
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Checksum accumulate (0x92)<br />
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<a href="#anchor12">2.2.8</a>
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Increment on read (0x93)<br />
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<a href="#anchor13">2.3</a>
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Tool Chain<br />
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Tool Chain<br />
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<a href="#anchor11">2.4</a>
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<a href="#anchor14">2.4</a>
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Tests<br />
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Tests<br />
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<a href="#tvs80">2.4.1</a>
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<a href="#tvs80">2.4.1</a>
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tvs80 test<br />
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tvs80 test<br />
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<a href="#rfc.references1">3.</a>
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<a href="#rfc.references1">3.</a>
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References<br />
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References<br />
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<p>
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<p>
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When set, starts a countdown (in clocks) until assertion of
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When set, starts a countdown (in clocks) until assertion of
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the INT_N signal.
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the INT_N signal.
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</p>
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</p>
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<a name="rfc.section.2.3"></a><h4><a name="anchor10">2.3</a> Tool Chain</h4>
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<a name="rfc.section.2.2.6"></a><h4><a name="anchor10">2.2.6</a> Checksum value (0x91)</h4>
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<p>This register holds the checksum value of all data
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written to the accumulate register. The checksum is a simple
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twos-complement checksum, so it can be compared with a CPU-generated
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checksum.
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</p>
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<p>This register is readable and writeable. Writing the register sets
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the current checksum value.
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</p>
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<a name="rfc.section.2.2.7"></a><h4><a name="anchor11">2.2.7</a> Checksum accumulate (0x92)</h4>
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<p>This write-only register adds the written value to the value
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contained in the Checksum Value register.
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</p>
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<a name="rfc.section.2.2.8"></a><h4><a name="anchor12">2.2.8</a> Increment on read (0x93)</h4>
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<p>This register increments every time it is read, so reading it
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repeatedly generates an incrementing sequence. It can be reset
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by writing it to a new starting value.
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</p>
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<a name="rfc.section.2.3"></a><h4><a name="anchor13">2.3</a> Tool Chain</h4>
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<p>The minimum toolchain required to simulate the tv80 is the
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<p>The minimum toolchain required to simulate the tv80 is the
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<a class="info" href="#cver">CVer<span>Vanvick, A., GPL Cver Simulator, .</span></a>[3] Verilog simulator, and the
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<a class="info" href="#cver">CVer<span>Vanvick, A., GPL Cver Simulator, .</span></a>[3] Verilog simulator, and the
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<a class="info" href="#sdcc">SDCC<span>, Small Device C Compiler, .</span></a>[2] compiler/assembler/linker. In
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<a class="info" href="#sdcc">SDCC<span>, Small Device C Compiler, .</span></a>[2] compiler/assembler/linker. In
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addition, to run the <a class="info" href="#tvs80">tvs80<span>tvs80 test</span></a> instruction
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addition, to run the <a class="info" href="#tvs80">tvs80<span>tvs80 test</span></a> instruction
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test suite, the <a class="info" href="#dosbox">DOSBox<span>, DOSBox, .</span></a>[4] DOS emulator
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test suite, the <a class="info" href="#dosbox">DOSBox<span>, DOSBox, .</span></a>[4] DOS emulator
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is required.
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is required.
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</p>
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</p>
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<a name="rfc.section.2.4"></a><h4><a name="anchor11">2.4</a> Tests</h4>
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<a name="rfc.section.2.4"></a><h4><a name="anchor14">2.4</a> Tests</h4>
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<p>Most of the tests in the tv80 environment are written in C, and should
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<p>Most of the tests in the tv80 environment are written in C, and should
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be compiled with the <a class="info" href="#sdcc">sdcc<span>, Small Device C Compiler, .</span></a>[2] compiler.
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be compiled with the <a class="info" href="#sdcc">sdcc<span>, Small Device C Compiler, .</span></a>[2] compiler.
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</p>
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</p>
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