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https://opencores.org/ocsvn/tv80/tv80/trunk
[/] [tv80/] [trunk/] [env/] [env_io.v] - Diff between revs 31 and 37
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| Rev 31 |
Rev 37 |
| Line 23... |
Line 23... |
reg [7:0] timeout_ctl;
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reg [7:0] timeout_ctl;
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reg [15:0] cur_timeout;
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reg [15:0] cur_timeout;
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reg [15:0] max_timeout;
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reg [15:0] max_timeout;
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reg [7:0] int_countdown;
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reg [7:0] int_countdown;
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reg [7:0] checksum;
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reg [7:0] ior_value; // increment-on-read value
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assign DI = (!iorq_n & !rd_n & io_cs) ? io_data : {8{1'bz}};
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assign DI = (!iorq_n & !rd_n & io_cs) ? io_data : {8{1'bz}};
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initial
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initial
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begin
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begin
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| Line 36... |
Line 38... |
max_timeout = 10000;
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max_timeout = 10000;
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timeout_ctl = 1;
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timeout_ctl = 1;
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int_countdown = 0;
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int_countdown = 0;
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end
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end
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always @*
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begin
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if (!iorq_n & !rd_n)
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begin
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io_cs = (addr[7:5] == 3'b100);
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case (addr)
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8'h83 : io_data = max_timeout[7:0];
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8'h84 : io_data = max_timeout[15:8];
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8'h90 : io_data = int_countdown;
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8'h91 : io_data = checksum;
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8'h93 : io_data = ior_value;
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default : io_data = 8'hzz;
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endcase // case(addr)
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end // if (!iorq_n & !rd_n)
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end // always @ *
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (!iorq_n & !wr_n)
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if (!iorq_n & !wr_n)
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case (addr)
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case (addr)
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8'h80 :
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8'h80 :
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| Line 84... |
Line 104... |
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8'h83 : max_timeout[7:0] = DO;
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8'h83 : max_timeout[7:0] = DO;
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8'h84 : max_timeout[15:8] = DO;
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8'h84 : max_timeout[15:8] = DO;
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8'h90 : int_countdown = DO;
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8'h90 : int_countdown = DO;
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8'h91 : checksum = DO;
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8'h92 : checksum = checksum + DO;
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8'h93 : ior_value = DO;
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endcase // case(addr)
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endcase // case(addr)
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end // always @ (posedge clk)
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end // always @ (posedge clk)
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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