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[/] [tv80/] [trunk/] [env/] [tb_top.v] - Diff between revs 84 and 89

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Rev 84	Rev 89
Line 1...	Line 1...
	`timescale 1ns/100ps
`define TV80_CORE_PATH tb_top.tv80s_inst.i_tv80_core	`define TV80_CORE_PATH tb_top.tv80s_inst.i_tv80_core

`module tb_top;`	`module tb_top;`

`reg clk;`	`reg clk;`
Line 16...	Line 17...
`wire rfsh_n;`	`wire rfsh_n;`
`wire halt_n;`	`wire halt_n;`
`wire busak_n;`	`wire busak_n;`
`wire [15:0] A;`	`wire [15:0] A;`
`wire [7:0] di;`	`wire [7:0] di;`
`wire [7:0] do;`	`wire [7:0] d_out;`
`wire ram_rd_cs, ram_wr_cs, rom_rd_cs;`	`wire ram_rd_cs, ram_wr_cs, rom_rd_cs;`
`reg tx_clk;`	`reg tx_clk;`

`always`	`always`
`begin`	`begin`
Line 52...	Line 53...
`.wr_n (wr_n),`	`.wr_n (wr_n),`
`.rfsh_n (rfsh_n),`	`.rfsh_n (rfsh_n),`
`.halt_n (halt_n),`	`.halt_n (halt_n),`
`.busak_n (busak_n),`	`.busak_n (busak_n),`
`.A (A[15:0]),`	`.A (A[15:0]),`
`.do (do[7:0]),`	`.dout (d_out[7:0]),`
`// Inputs`	`// Inputs`
`.reset_n (reset_n),`	`.reset_n (reset_n),`
`.clk (clk),`	`.clk (clk),`
`.wait_n (wait_n),`	`.wait_n (wait_n),`
`.int_n (int_n),`	`.int_n (int_n),`
Line 68...	Line 69...
`(`	`(`
`// Outputs`	`// Outputs`
`.rd_data (di),`	`.rd_data (di),`
`// Inputs`	`// Inputs`
`.wr_clk (clk),`	`.wr_clk (clk),`
`.wr_data (do),`	`.wr_data (d_out),`
`.wr_cs (ram_wr_cs),`	`.wr_cs (ram_wr_cs),`
`.addr (A[14:0]),`	`.addr (A[14:0]),`
`.rd_cs (ram_rd_cs));`	`.rd_cs (ram_rd_cs));`

`async_mem rom`	`async_mem rom`
Line 94...	Line 95...
`.clk (clk),`	`.clk (clk),`
`.iorq_n (iorq_n),`	`.iorq_n (iorq_n),`
`.rd_n (rd_n),`	`.rd_n (rd_n),`
`.wr_n (wr_n),`	`.wr_n (wr_n),`
`.addr (A[7:0]),`	`.addr (A[7:0]),`
`.DO (do[7:0]));`	`.D_OUT (d_out[7:0]));`

`//----------------------------------------------------------------------`	`//----------------------------------------------------------------------`
`// UART`	`// UART`
`//----------------------------------------------------------------------`	`//----------------------------------------------------------------------`

`wire uart_cs_n;`	`wire uart_cs_n;`
`wire [7:0] uart_rd_data;`	`wire [7:0] uart_rd_data;`

`wire sin;`	`wire ser_in;`
`wire cts_n;`	`wire cts_n;`
`wire dsr_n;`	`wire dsr_n;`
`wire ri_n;`	`wire ri_n;`
`wire dcd_n;`	`wire dcd_n;`

Line 121...	Line 122...

`// base address of 0x18 (24dec)`	`// base address of 0x18 (24dec)`

`assign uart_cs_n = ~(!iorq_n & (A[7:3] == 5'h3));`	`assign uart_cs_n = ~(!iorq_n & (A[7:3] == 5'h3));`
`assign di = (!uart_cs_n & !rd_n) ? uart_rd_data : 8'bz;`	`assign di = (!uart_cs_n & !rd_n) ? uart_rd_data : 8'bz;`
`assign sin = sout;`	`assign ser_in = sout;`

`T16450 uart0`	`T16450 uart0`
`(.reset_n (reset_n),`	`(.reset_n (reset_n),`
`.clk (clk),`	`.clk (clk),`
`.rclk (baudout),`	`.rclk (baudout),`
`.cs_n (uart_cs_n),`	`.cs_n (uart_cs_n),`
`.rd_n (rd_n),`	`.rd_n (rd_n),`
`.wr_n (wr_n),`	`.wr_n (wr_n),`
`.addr (A[2:0]),`	`.addr (A[2:0]),`
`.wr_data (do),`	`.wr_data (d_out),`
`.rd_data (uart_rd_data),`	`.rd_data (uart_rd_data),`
`.sin (sin),`	`.sin (ser_in),`
`.cts_n (cts_n),`	`.cts_n (cts_n),`
`.dsr_n (dsr_n),`	`.dsr_n (dsr_n),`
`.ri_n (ri_n),`	`.ri_n (ri_n),`
`.dcd_n (dcd_n),`	`.dcd_n (dcd_n),`
`.sout (sout),`	`.sout (sout),`
Line 188...	Line 189...
`//.io_select (nwintf_sel),`	`//.io_select (nwintf_sel),`
`.iorq_n (iorq_n),`	`.iorq_n (iorq_n),`
`.rd_n (rd_n),`	`.rd_n (rd_n),`
`.wr_n (wr_n),`	`.wr_n (wr_n),`
`.addr (A[15:0]),`	`.addr (A[15:0]),`
`.wr_data (do));`	`.wr_data (d_out));`

`//----------------------------------------------------------------------`	`//----------------------------------------------------------------------`
`// Global Initialization`	`// Global Initialization`
`//----------------------------------------------------------------------`	`//----------------------------------------------------------------------`

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[/] [tv80/] [trunk/] [env/] [tb_top.v] - Diff between revs 84 and 89