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https://opencores.org/ocsvn/tv80/tv80/trunk
[/] [tv80/] [trunk/] [env/] [tb_top.v] - Diff between revs 42 and 53
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Rev 42 |
Rev 53 |
Line 87... |
Line 87... |
.rd_n (rd_n),
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.rd_n (rd_n),
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.wr_n (wr_n),
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.wr_n (wr_n),
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.addr (A[7:0]),
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.addr (A[7:0]),
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.DO (do[7:0]));
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.DO (do[7:0]));
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wire nwintf_sel = !iorq_n & (A[7:3] == 5'b00001);
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wire [7:0] rx_data, tx_data;
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wire rx_clk, rx_dv, rx_er;
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wire tx_dv, tx_er;
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wire tx_clk;
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wire [7:0] nw_data_out;
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// loopback config
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assign rx_data = tx_data;
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assign rx_dv = tx_dv;
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assign rx_er = tx_er;
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assign rx_clk = tx_clk;
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assign di = (nwintf_sel & !rd_n) ? nw_data_out : 8'bz;
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simple_gmii nwintf
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(
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// Outputs
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.tx_dv (tx_dv),
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.tx_er (tx_er),
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.tx_data (tx_data),
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.tx_clk (tx_clk),
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.io_data_out (nw_data_out),
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// Inputs
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.clk (clk),
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.reset (!reset_n),
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.rx_data (rx_data),
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.rx_clk (rx_clk),
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.rx_dv (rx_dv),
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.rx_er (rx_er),
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.io_select (nwintf_sel),
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.rd_n (rd_n),
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.wr_n (wr_n),
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.io_addr (A[2:0]),
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.io_data_in (do));
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initial
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initial
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begin
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begin
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clear_ram;
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clear_ram;
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reset_n = 0;
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reset_n = 0;
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wait_n = 1;
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wait_n = 1;
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