URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk/] [env/] [tb_top.v] - Diff between revs 53 and 56

Rev 53	Rev 56
Line 18...	Line 18...
`wire busak_n;`	`wire busak_n;`
`wire [15:0] A;`	`wire [15:0] A;`
`wire [7:0] di;`	`wire [7:0] di;`
`wire [7:0] do;`	`wire [7:0] do;`
`wire ram_rd_cs, ram_wr_cs, rom_rd_cs;`	`wire ram_rd_cs, ram_wr_cs, rom_rd_cs;`
	`reg tx_clk;`

`always`	`always`
`begin`	`begin`
`clk = 1;`	`clk = 1;`
`#5;`	`#5;`
`clk = 0;`	`clk = 0;`
`#5;`	`#5;`
`end`	`end`

	`always`
	`begin`
	`tx_clk = 0;`
	`#8;`
	`tx_clk = 1;`
	`#8;`
	`end`

`assign rom_rd_cs = !mreq_n & !rd_n & !A[15];`	`assign rom_rd_cs = !mreq_n & !rd_n & !A[15];`
`assign ram_rd_cs = !mreq_n & !rd_n & A[15];`	`assign ram_rd_cs = !mreq_n & !rd_n & A[15];`
`assign ram_wr_cs = !mreq_n & !wr_n & A[15];`	`assign ram_wr_cs = !mreq_n & !wr_n & A[15];`

`tv80s tv80s_inst`	`tv80s tv80s_inst`
Line 91...	Line 100...

`wire nwintf_sel = !iorq_n & (A[7:3] == 5'b00001);`	`wire nwintf_sel = !iorq_n & (A[7:3] == 5'b00001);`
`wire [7:0] rx_data, tx_data;`	`wire [7:0] rx_data, tx_data;`
`wire rx_clk, rx_dv, rx_er;`	`wire rx_clk, rx_dv, rx_er;`
`wire tx_dv, tx_er;`	`wire tx_dv, tx_er;`
`wire tx_clk;`
`wire [7:0] nw_data_out;`	`wire [7:0] nw_data_out;`

`// loopback config`	`// loopback config`
`assign rx_data = tx_data;`	`assign rx_data = tx_data;`
`assign rx_dv = tx_dv;`	`assign rx_dv = tx_dv;`