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https://opencores.org/ocsvn/tv80/tv80/trunk
[/] [tv80/] [trunk/] [env/] [tb_top.v] - Diff between revs 66 and 69
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| Rev 66 |
Rev 69 |
| Line 96... |
Line 96... |
.rd_n (rd_n),
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.rd_n (rd_n),
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.wr_n (wr_n),
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.wr_n (wr_n),
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.addr (A[7:0]),
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.addr (A[7:0]),
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.DO (do[7:0]));
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.DO (do[7:0]));
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wire nwintf_sel = !iorq_n & (A[7:3] == 5'b00001);
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//----------------------------------------------------------------------
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// UART
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//----------------------------------------------------------------------
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wire uart_cs_n;
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wire [7:0] uart_rd_data;
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wire sin;
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wire cts_n;
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wire dsr_n;
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wire ri_n;
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wire dcd_n;
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wire sout;
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wire rts_n;
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wire dtr_n;
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wire out1_n;
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wire out2_n;
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wire baudout;
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wire intr;
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// base address of 0x18 (24dec)
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assign uart_cs_n = ~(!iorq_n & (A[7:3] == 5'h3));
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assign di = (!uart_cs_n & !rd_n) ? uart_rd_data : 8'bz;
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assign sin = sout;
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T16450 uart0
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(.reset_n (reset_n),
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.clk (clk),
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.rclk (baudout),
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.cs_n (uart_cs_n),
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.rd_n (rd_n),
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.wr_n (wr_n),
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.addr (A[2:0]),
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.wr_data (do),
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.rd_data (uart_rd_data),
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.sin (sin),
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.cts_n (cts_n),
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.dsr_n (dsr_n),
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.ri_n (ri_n),
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.dcd_n (dcd_n),
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.sout (sout),
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.rts_n (rts_n),
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.dtr_n (dtr_n),
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.out1_n (out1_n),
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.out2_n (out2_n),
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.baudout (baudout),
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.intr (intr));
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//----------------------------------------------------------------------
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// Network Interface
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//----------------------------------------------------------------------
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//wire nwintf_sel = !iorq_n & (A[7:3] == 5'b00001);
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wire [7:0] rx_data, tx_data;
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wire [7:0] rx_data, tx_data;
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wire rx_clk, rx_dv, rx_er;
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wire rx_clk, rx_dv, rx_er;
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wire tx_dv, tx_er;
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wire tx_dv, tx_er;
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wire [7:0] nw_data_out;
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wire [7:0] nw_data_out;
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wire nwintf_oe;
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wire nwintf_oe;
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| Line 111... |
Line 165... |
assign rx_er = tx_er;
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assign rx_er = tx_er;
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assign rx_clk = tx_clk;
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assign rx_clk = tx_clk;
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assign di = (nwintf_oe) ? nw_data_out : 8'bz;
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assign di = (nwintf_oe) ? nw_data_out : 8'bz;
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`ifdef OLD_INTERFACE
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simple_gmii nwintf
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(
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// Outputs
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.tx_dv (tx_dv),
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.tx_er (tx_er),
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.tx_data (tx_data),
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.tx_clk (tx_clk),
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.io_data_out (nw_data_out),
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// Inputs
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.clk (clk),
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.reset (!reset_n),
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.rx_data (rx_data),
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.rx_clk (rx_clk),
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.rx_dv (rx_dv),
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.rx_er (rx_er),
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.io_select (nwintf_sel),
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.rd_n (rd_n),
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.wr_n (wr_n),
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.io_addr (A[2:0]),
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.io_data_in (do));
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`else // !`ifdef OLD_INTERFACE
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simple_gmii_top nwintf
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simple_gmii_top nwintf
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(
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(
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// unused outputs
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// unused outputs
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.int_n (),
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.int_n (),
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// Outputs
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// Outputs
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| Line 157... |
Line 189... |
.iorq_n (iorq_n),
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.iorq_n (iorq_n),
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.rd_n (rd_n),
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.rd_n (rd_n),
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.wr_n (wr_n),
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.wr_n (wr_n),
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.addr (A[15:0]),
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.addr (A[15:0]),
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.wr_data (do));
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.wr_data (do));
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`endif // !`ifdef OLD_INTERFACE
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//----------------------------------------------------------------------
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// Global Initialization
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//----------------------------------------------------------------------
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initial
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initial
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begin
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begin
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clear_ram;
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clear_ram;
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reset_n = 0;
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reset_n = 0;
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