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| Rev 105 |
Rev 109 |
| Line 71... |
Line 71... |
wire [1:0] fw_up_ctrl;
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wire [1:0] fw_up_ctrl;
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wire dma_iorq_n;
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wire dma_iorq_n;
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wire [7:0] dma_rd_data;
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wire [7:0] dma_rd_data;
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reg [31:0] read_hold;
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reg [31:0] read_hold;
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reg read_latch;
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reg read_latch;
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wire dma_int_n; // From dma of mx_lcfg_dma.v
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wire proc_reset_n;
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wire proc_reset_n;
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [7:0] cd_rdata; // From cfgo_driver of lcfg_cfgo_driver.v
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wire [7:0] cd_rdata; // From cfgo_driver of lcfg_cfgo_driver.v
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wire cfgo_wait_n; // From cfgo_driver of lcfg_cfgo_driver.v
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wire cfgo_wait_n; // From cfgo_driver of lcfg_cfgo_driver.v
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| Line 99... |
Line 98... |
.A (addr),
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.A (addr),
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// Inputs
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// Inputs
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.reset_n (proc_reset_n),
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.reset_n (proc_reset_n),
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.clk (clk),
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.clk (clk),
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.wait_n (wait_n),
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.wait_n (wait_n),
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.int_n (dma_int_n),
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.int_n (1'b1),
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.nmi_n (1'b1),
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.nmi_n (1'b1),
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.busrq_n (1'b1),
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.busrq_n (1'b1),
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.di (di));
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.di (di));
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always @(posedge clk)
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always @(posedge clk)
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| Line 206... |
Line 205... |
// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset_n (reset_n),
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.reset_n (reset_n),
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.addr (addr[15:0]),
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.addr (addr[15:0]),
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.cd_wdata (dout[7:0]), // Templated
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.cd_wdata (dout[7:0]), // Templated
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.mreq_n (mreq_n),
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.rd_n (rd_n),
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.rd_n (rd_n),
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.wr_n (wr_n),
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.wr_n (wr_n),
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.iorq_n (iorq_n),
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.iorq_n (iorq_n),
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.cfgo_trdy (cfgo_trdy),
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.cfgo_trdy (cfgo_trdy),
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.cfgo_rd_data (cfgo_rd_data[31:0]));
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.cfgo_rd_data (cfgo_rd_data[31:0]));
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