| Line 14... |
Line 14... |
(/*AUTOARG*/
|
(/*AUTOARG*/
|
// Outputs
|
// Outputs
|
cd_rdata, cfgo_wait_n, cfgo_irdy, cfgo_addr, cfgo_write,
|
cd_rdata, cfgo_wait_n, cfgo_irdy, cfgo_addr, cfgo_write,
|
cfgo_wr_data,
|
cfgo_wr_data,
|
// Inputs
|
// Inputs
|
clk, reset_n, addr, cd_wdata, mreq_n, rd_n, wr_n, iorq_n, cfgo_trdy,
|
clk, reset_n, addr, cd_wdata, rd_n, wr_n, iorq_n, cfgo_trdy,
|
cfgo_rd_data
|
cfgo_rd_data
|
);
|
);
|
|
|
parameter io_base_addr = 0;
|
parameter io_base_addr = 0;
|
input clk;
|
input clk;
|
| Line 27... |
Line 27... |
// TV80 processor interface
|
// TV80 processor interface
|
input [15:0] addr;
|
input [15:0] addr;
|
output [7:0] cd_rdata;
|
output [7:0] cd_rdata;
|
input [7:0] cd_wdata;
|
input [7:0] cd_wdata;
|
|
|
input mreq_n;
|
|
input rd_n, wr_n;
|
input rd_n, wr_n;
|
input iorq_n;
|
input iorq_n;
|
output cfgo_wait_n;
|
output cfgo_wait_n;
|
|
|
// outgoing config interface to system
|
// outgoing config interface to system
|
| Line 60... |
Line 59... |
parameter s_idle = 0, s_write = 1, s_read = 2, s_ack = 3;
|
parameter s_idle = 0, s_write = 1, s_read = 2, s_ack = 3;
|
|
|
reg [31:0] chold, nxt_chold;
|
reg [31:0] chold, nxt_chold;
|
reg [3:0] state, nxt_state;
|
reg [3:0] state, nxt_state;
|
|
|
assign rf_irdy = !mreq_n & !iorq_n & ((addr[7:0] & 8'hF8) == io_base_addr);
|
assign rf_irdy = !iorq_n & ((addr[7:0] & 8'hF8) == io_base_addr);
|
assign rf_write = ~wr_n;
|
assign rf_write = ~wr_n;
|
assign cfgo_addr = { cfg_addr1, cfg_addr0 };
|
assign cfgo_addr = { cfg_addr1, cfg_addr0 };
|
assign cfgo_wr_data = chold;
|
assign cfgo_wr_data = chold;
|
assign cfgo_irdy = state[s_write] | state[s_read];
|
assign cfgo_irdy = state[s_write] | state[s_read];
|
assign cfgo_write = state[s_write];
|
assign cfgo_write = state[s_write];
|
