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https://opencores.org/ocsvn/tv80/tv80/trunk
[/] [tv80/] [trunk/] [rtl/] [core/] [tv80_core.v] - Diff between revs 87 and 88
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| Rev 87 |
Rev 88 |
| Line 300... |
Line 300... |
default : number_to_bitvec = 7'bx;
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default : number_to_bitvec = 7'bx;
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endcase // case(num)
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endcase // case(num)
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end
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end
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endfunction // number_to_bitvec
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endfunction // number_to_bitvec
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function [2:0] mcyc_to_number;
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input [6:0] mcyc;
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begin
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casez (mcyc)
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7'b1zzzzzz : mcyc_to_number = 3'h7;
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7'bz1zzzzz : mcyc_to_number = 3'h6;
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7'bzz1zzzz : mcyc_to_number = 3'h5;
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7'bzzz1zzz : mcyc_to_number = 3'h4;
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7'bzzzz1zz : mcyc_to_number = 3'h3;
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7'bzzzzz1z : mcyc_to_number = 3'h2;
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7'bzzzzzz1 : mcyc_to_number = 3'h1;
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default : mcyc_to_number = 3'h1;
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endcase
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end
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endfunction
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always @(/*AUTOSENSE*/mcycle or mcycles or tstate or tstates)
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always @(/*AUTOSENSE*/mcycle or mcycles or tstate or tstates)
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begin
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begin
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case (mcycles)
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case (mcycles)
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1 : last_mcycle = mcycle[0];
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1 : last_mcycle = mcycle[0];
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2 : last_mcycle = mcycle[1];
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2 : last_mcycle = mcycle[1];
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| Line 1247... |
Line 1263... |
begin
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begin
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tstate <= #1 7'b0000010;
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tstate <= #1 7'b0000010;
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if (NextIs_XY_Fetch == 1'b1 )
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if (NextIs_XY_Fetch == 1'b1 )
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begin
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begin
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mcycle <= #1 7'b0100000;
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mcycle <= #1 7'b0100000;
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Pre_XY_F_M <= #1 mcycle;
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Pre_XY_F_M <= #1 mcyc_to_number(mcycle);
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if (IR == 8'b00110110 && Mode == 0 )
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if (IR == 8'b00110110 && Mode == 0 )
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begin
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begin
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Pre_XY_F_M <= #1 3'b010;
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Pre_XY_F_M <= #1 3'b010;
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end
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end
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end
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end
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