URL
https://opencores.org/ocsvn/tv80/tv80/trunk
[/] [tv80/] [trunk/] [rtl/] [core/] [tv80_core.v] - Diff between revs 87 and 88
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 87 |
Rev 88 |
Line 300... |
Line 300... |
default : number_to_bitvec = 7'bx;
|
default : number_to_bitvec = 7'bx;
|
endcase // case(num)
|
endcase // case(num)
|
end
|
end
|
endfunction // number_to_bitvec
|
endfunction // number_to_bitvec
|
|
|
|
function [2:0] mcyc_to_number;
|
|
input [6:0] mcyc;
|
|
begin
|
|
casez (mcyc)
|
|
7'b1zzzzzz : mcyc_to_number = 3'h7;
|
|
7'bz1zzzzz : mcyc_to_number = 3'h6;
|
|
7'bzz1zzzz : mcyc_to_number = 3'h5;
|
|
7'bzzz1zzz : mcyc_to_number = 3'h4;
|
|
7'bzzzz1zz : mcyc_to_number = 3'h3;
|
|
7'bzzzzz1z : mcyc_to_number = 3'h2;
|
|
7'bzzzzzz1 : mcyc_to_number = 3'h1;
|
|
default : mcyc_to_number = 3'h1;
|
|
endcase
|
|
end
|
|
endfunction
|
|
|
always @(/*AUTOSENSE*/mcycle or mcycles or tstate or tstates)
|
always @(/*AUTOSENSE*/mcycle or mcycles or tstate or tstates)
|
begin
|
begin
|
case (mcycles)
|
case (mcycles)
|
1 : last_mcycle = mcycle[0];
|
1 : last_mcycle = mcycle[0];
|
2 : last_mcycle = mcycle[1];
|
2 : last_mcycle = mcycle[1];
|
Line 1247... |
Line 1263... |
begin
|
begin
|
tstate <= #1 7'b0000010;
|
tstate <= #1 7'b0000010;
|
if (NextIs_XY_Fetch == 1'b1 )
|
if (NextIs_XY_Fetch == 1'b1 )
|
begin
|
begin
|
mcycle <= #1 7'b0100000;
|
mcycle <= #1 7'b0100000;
|
Pre_XY_F_M <= #1 mcycle;
|
Pre_XY_F_M <= #1 mcyc_to_number(mcycle);
|
if (IR == 8'b00110110 && Mode == 0 )
|
if (IR == 8'b00110110 && Mode == 0 )
|
begin
|
begin
|
Pre_XY_F_M <= #1 3'b010;
|
Pre_XY_F_M <= #1 3'b010;
|
end
|
end
|
end
|
end
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.