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[/] [tv80/] [trunk/] [rtl/] [core/] [tv80_core.v] - Diff between revs 88 and 89

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Line 22...	Line 22...
`// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE`	`// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE`
`// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.`	`// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.`

`module tv80_core (/AUTOARG/`	`module tv80_core (/AUTOARG/`
`// Outputs`	`// Outputs`
`m1_n, iorq, no_read, write, rfsh_n, halt_n, busak_n, A, do, mc, ts,`	`m1_n, iorq, no_read, write, rfsh_n, halt_n, busak_n, A, dout, mc, ts,`
`intcycle_n, IntE, stop,`	`intcycle_n, IntE, stop,`
`// Inputs`	`// Inputs`
`reset_n, clk, cen, wait_n, int_n, nmi_n, busrq_n, dinst, di`	`reset_n, clk, cen, wait_n, int_n, nmi_n, busrq_n, dinst, di`
`);`	`);`
`// Beginning of automatic inputs (from unused autoinst inputs)`	`// Beginning of automatic inputs (from unused autoinst inputs)`
Line 58...	Line 58...
`output halt_n;`	`output halt_n;`
`output busak_n;`	`output busak_n;`
`output [15:0] A;`	`output [15:0] A;`
`input [7:0] dinst;`	`input [7:0] dinst;`
`input [7:0] di;`	`input [7:0] di;`
`output [7:0] do;`	`output [7:0] dout;`
`output [6:0] mc;`	`output [6:0] mc;`
`output [6:0] ts;`	`output [6:0] ts;`
`output intcycle_n;`	`output intcycle_n;`
`output IntE;`	`output IntE;`
`output stop;`	`output stop;`
Line 73...	Line 73...
`reg rfsh_n;`	`reg rfsh_n;`
`endif	`endif
`reg halt_n;`	`reg halt_n;`
`reg busak_n;`	`reg busak_n;`
`reg [15:0] A;`	`reg [15:0] A;`
`reg [7:0] do;`	`reg [7:0] dout;`
`reg [6:0] mc;`	`reg [6:0] mc;`
`reg [6:0] ts;`	`reg [6:0] ts;`
`reg intcycle_n;`	`reg intcycle_n;`
`reg IntE;`	`reg IntE;`
`reg stop;`	`reg stop;`
Line 368...	Line 368...
`Save_Mux = DI_Reg;`	`Save_Mux = DI_Reg;`
`else`	`else`
`Save_Mux = ALU_Q;`	`Save_Mux = ALU_Q;`
`end // always @ *`	`end // always @ *`

`always @ (posedge clk)`	`always @ (posedge clk or negedge reset_n)`
`begin`	`begin`
`if (reset_n == 1'b0 )`	`if (reset_n == 1'b0 )`
`begin`	`begin`
`PC <= #1 0; // Program Counter`	`PC <= #1 0; // Program Counter`
`A <= #1 0;`	`A <= #1 0;`
Line 380...	Line 380...
`IR <= #1 8'b00000000;`	`IR <= #1 8'b00000000;`
`ISet <= #1 2'b00;`	`ISet <= #1 2'b00;`
`XY_State <= #1 2'b00;`	`XY_State <= #1 2'b00;`
`IStatus <= #1 2'b00;`	`IStatus <= #1 2'b00;`
`mcycles <= #1 3'b000;`	`mcycles <= #1 3'b000;`
`do <= #1 8'b00000000;`	`dout <= #1 8'b00000000;`

`ACC <= #1 8'hFF;`	`ACC <= #1 8'hFF;`
`F <= #1 8'hFF;`	`F <= #1 8'hFF;`
`Ap <= #1 8'hFF;`	`Ap <= #1 8'hFF;`
`Fp <= #1 8'hFF;`	`Fp <= #1 8'hFF;`
Line 455...	Line 455...
`IR <= #1 8'b11111111;`	`IR <= #1 8'b11111111;`
`end`	`end`
`else if (Halt_FF == 1'b1 \|\| (IntCycle == 1'b1 && IStatus == 2'b10) \|\| NMICycle == 1'b1 )`	`else if (Halt_FF == 1'b1 \|\| (IntCycle == 1'b1 && IStatus == 2'b10) \|\| NMICycle == 1'b1 )`
`begin`	`begin`
`IR <= #1 8'b00000000;`	`IR <= #1 8'b00000000;`
	`TmpAddr[7:0] <= #1 dinst; // Special M1 vector fetch`
`end`	`end`
`else`	`else`
`begin`	`begin`
`IR <= #1 dinst;`	`IR <= #1 dinst;`
`end`	`end`
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`end // if (T_Res == 1'b1 && I_INRC == 1'b1 )`	`end // if (T_Res == 1'b1 && I_INRC == 1'b1 )`


`if (tstate[1] && Auto_Wait_t1 == 1'b0 )`	`if (tstate[1] && Auto_Wait_t1 == 1'b0 )`
`begin`	`begin`
`do <= #1 BusB;`	`dout <= #1 BusB;`
`if (I_RLD == 1'b1 )`	`if (I_RLD == 1'b1 )`
`begin`	`begin`
`do[3:0] <= #1 BusA[3:0];`	`dout[3:0] <= #1 BusA[3:0];`
`do[7:4] <= #1 BusB[3:0];`	`dout[7:4] <= #1 BusB[3:0];`
`end`	`end`
`if (I_RRD == 1'b1 )`	`if (I_RRD == 1'b1 )`
`begin`	`begin`
`do[3:0] <= #1 BusB[7:4];`	`dout[3:0] <= #1 BusB[7:4];`
`do[7:4] <= #1 BusA[3:0];`	`dout[7:4] <= #1 BusA[3:0];`
`end`	`end`
`end`	`end`

`if (T_Res == 1'b1 )`	`if (T_Res == 1'b1 )`
`begin`	`begin`
Line 845...	Line 846...
`begin`	`begin`
`case (Read_To_Reg_r)`	`case (Read_To_Reg_r)`
`5'b10111 :`	`5'b10111 :`
`ACC <= #1 Save_Mux;`	`ACC <= #1 Save_Mux;`
`5'b10110 :`	`5'b10110 :`
`do <= #1 Save_Mux;`	`dout <= #1 Save_Mux;`
`5'b11000 :`	`5'b11000 :`
`SP[7:0] <= #1 Save_Mux;`	`SP[7:0] <= #1 Save_Mux;`
`5'b11001 :`	`5'b11001 :`
`SP[15:8] <= #1 Save_Mux;`	`SP[15:8] <= #1 Save_Mux;`
`5'b11011 :`	`5'b11011 :`
Line 1096...	Line 1097...
`//`	`//`
`// Generate external control signals`	`// Generate external control signals`
`//`	`//`
`//-------------------------------------------------------------------------`	`//-------------------------------------------------------------------------`
`ifdef TV80_REFRESH	`ifdef TV80_REFRESH
`always @ (posedge clk)`	`always @ (posedge clk or negedge reset_n)`
`begin`	`begin`
`if (reset_n == 1'b0 )`	`if (reset_n == 1'b0 )`
`begin`	`begin`
`rfsh_n <= #1 1'b1;`	`rfsh_n <= #1 1'b1;`
`end`	`end`
Line 1141...	Line 1142...
`//`	`//`
`// Syncronise inputs`	`// Syncronise inputs`
`//`	`//`
`//-----------------------------------------------------------------------`	`//-----------------------------------------------------------------------`

`always @ (posedge clk)`	`always @ (posedge clk or negedge reset_n)`
`begin : sync_inputs`	`begin : sync_inputs`
	`if (~reset_n)`
`if (reset_n == 1'b0 )`
`begin`	`begin`
`BusReq_s <= #1 1'b0;`	`BusReq_s <= #1 1'b0;`
`INT_s <= #1 1'b0;`	`INT_s <= #1 1'b0;`
`NMI_s <= #1 1'b0;`	`NMI_s <= #1 1'b0;`
`Oldnmi_n <= #1 1'b0;`	`Oldnmi_n <= #1 1'b0;`
Line 1176...	Line 1176...
`//`	`//`
`// Main state machine`	`// Main state machine`
`//`	`//`
`//-----------------------------------------------------------------------`	`//-----------------------------------------------------------------------`

`always @ (posedge clk)`	`always @ (posedge clk or negedge reset_n)`
`begin`	`begin`
`if (reset_n == 1'b0 )`	`if (reset_n == 1'b0 )`
`begin`	`begin`
`mcycle <= #1 7'b0000001;`	`mcycle <= #1 7'b0000001;`
`tstate <= #1 7'b0000001;`	`tstate <= #1 7'b0000001;`
Line 1204...	Line 1204...
`begin`	`begin`
`Auto_Wait_t1 <= #1 1'b0;`	`Auto_Wait_t1 <= #1 1'b0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`Auto_Wait_t1 <= #1 Auto_Wait \|\| iorq_i;`	`Auto_Wait_t1 <= #1 Auto_Wait \|\| (iorq_i & ~Auto_Wait_t2);`
`end`	`end`
`Auto_Wait_t2 <= #1 Auto_Wait_t1;`	`Auto_Wait_t2 <= #1 Auto_Wait_t1 & !T_Res;`
`No_BTR <= #1 (I_BT && (~ IR[4] \|\| ~ F[Flag_P])) \|\|`	`No_BTR <= #1 (I_BT && (~ IR[4] \|\| ~ F[Flag_P])) \|\|`
`(I_BC && (~ IR[4] \|\| F[Flag_Z] \|\| ~ F[Flag_P])) \|\|`	`(I_BC && (~ IR[4] \|\| F[Flag_Z] \|\| ~ F[Flag_P])) \|\|`
`(I_BTR && (~ IR[4] \|\| F[Flag_Z]));`	`(I_BTR && (~ IR[4] \|\| F[Flag_Z]));`
`if (tstate[2] )`	`if (tstate[2] )`
`begin`	`begin`
`if (SetEI == 1'b1 )`	`if (SetEI == 1'b1 )`
`begin`	`begin`
	`if (!NMICycle)`
`IntE_FF1 <= #1 1'b1;`	`IntE_FF1 <= #1 1'b1;`
`IntE_FF2 <= #1 1'b1;`	`IntE_FF2 <= #1 1'b1;`
`end`	`end`
`if (I_RETN == 1'b1 )`	`if (I_RETN == 1'b1 )`
`begin`	`begin`
Line 1371...	Line 1372...
`Auto_Wait = 1'b1;`	`Auto_Wait = 1'b1;`
`end`	`end`
`end`	`end`
`end // always @ *`	`end // always @ *`

`// synopsys dc_script_begin`
`// set_attribute current_design "revision" "$Id: tv80_core.v,v 1.5 2005-01-26 18:55:47 ghutchis Exp $" -type string -quiet`
`// synopsys dc_script_end`
`endmodule // T80`	`endmodule // T80`


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[/] [tv80/] [trunk/] [rtl/] [core/] [tv80_core.v] - Diff between revs 88 and 89