| Line 305... |
Line 305... |
function [2:0] mcyc_to_number;
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function [2:0] mcyc_to_number;
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input [6:0] mcyc;
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input [6:0] mcyc;
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begin
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begin
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casez (mcyc)
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casez (mcyc)
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7'b1zzzzzz : mcyc_to_number = 3'h7;
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7'b1zzzzzz : mcyc_to_number = 3'h7;
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7'bz1zzzzz : mcyc_to_number = 3'h6;
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7'b01zzzzz : mcyc_to_number = 3'h6;
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7'bzz1zzzz : mcyc_to_number = 3'h5;
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7'b001zzzz : mcyc_to_number = 3'h5;
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7'bzzz1zzz : mcyc_to_number = 3'h4;
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7'b0001zzz : mcyc_to_number = 3'h4;
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7'bzzzz1zz : mcyc_to_number = 3'h3;
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7'b00001zz : mcyc_to_number = 3'h3;
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7'bzzzzz1z : mcyc_to_number = 3'h2;
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7'b000001z : mcyc_to_number = 3'h2;
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7'bzzzzzz1 : mcyc_to_number = 3'h1;
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7'b0000001 : mcyc_to_number = 3'h1;
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default : mcyc_to_number = 3'h1;
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default : mcyc_to_number = 3'h1;
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endcase
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endcase
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end
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end
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endfunction
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endfunction
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| Line 853... |
Line 853... |
SP[7:0] <= #1 Save_Mux;
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SP[7:0] <= #1 Save_Mux;
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5'b11001 :
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5'b11001 :
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SP[15:8] <= #1 Save_Mux;
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SP[15:8] <= #1 Save_Mux;
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5'b11011 :
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5'b11011 :
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F <= #1 Save_Mux;
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F <= #1 Save_Mux;
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default : ;
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endcase
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endcase
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end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...
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end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...
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end // if (ClkEn == 1'b1 )
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end // if (ClkEn == 1'b1 )
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end // else: !if(reset_n == 1'b0 )
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end // else: !if(reset_n == 1'b0 )
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end
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end
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| Line 952... |
Line 953... |
case (Read_To_Reg_r)
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case (Read_To_Reg_r)
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5'b10000 , 5'b10001 , 5'b10010 , 5'b10011 , 5'b10100 , 5'b10101 :
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5'b10000 , 5'b10001 , 5'b10010 , 5'b10011 , 5'b10100 , 5'b10101 :
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begin
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begin
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RegWEH = ~ Read_To_Reg_r[0];
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RegWEH = ~ Read_To_Reg_r[0];
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RegWEL = Read_To_Reg_r[0];
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RegWEL = Read_To_Reg_r[0];
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end
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end // UNMATCHED !!
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default : ;
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endcase // case(Read_To_Reg_r)
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endcase // case(Read_To_Reg_r)
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end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...
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end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...
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| Line 964... |
Line 966... |
begin
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begin
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RegWEH = 1'b1;
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RegWEH = 1'b1;
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RegWEL = 1'b1;
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RegWEL = 1'b1;
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end
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end
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if (IncDec_16[2] == 1'b1 && ((tstate[2] && wait_n == 1'b1 && mcycle != 3'b001) || (tstate[3] && mcycle[0])) )
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if (IncDec_16[2] && ((tstate[2] && ~wait_n && ~mcycle[0]) || (tstate[3] && mcycle[0])) )
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begin
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begin
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case (IncDec_16[1:0])
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case (IncDec_16[1:0])
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2'b00 , 2'b01 , 2'b10 :
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2'b00 , 2'b01 , 2'b10 :
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begin
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begin
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RegWEH = 1'b1;
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RegWEH = 1'b1;
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RegWEL = 1'b1;
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RegWEL = 1'b1;
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end
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end // UNMATCHED !!
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default : ;
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endcase
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endcase
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end
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end
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end // always @ *
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end // always @ *
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| Line 993... |
Line 996... |
else if (ExchangeDH == 1'b1 && tstate[4] )
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else if (ExchangeDH == 1'b1 && tstate[4] )
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begin
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begin
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RegDIH = RegBusA_r[15:8];
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RegDIH = RegBusA_r[15:8];
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RegDIL = RegBusA_r[7:0];
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RegDIL = RegBusA_r[7:0];
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end
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end
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else if (IncDec_16[2] == 1'b1 && ((tstate[2] && mcycle != 3'b001) || (tstate[3] && mcycle[0])) )
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else if (IncDec_16[2] == 1'b1 && ((tstate[2] && ~mcycle[0]) || (tstate[3] && mcycle[0])) )
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begin
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begin
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RegDIH = ID16[15:8];
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RegDIH = ID16[15:8];
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RegDIL = ID16[7:0];
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RegDIL = ID16[7:0];
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end
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end
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end
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end
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