URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk/] [rtl/] [core/] [tv80_mcode.v] - Diff between revs 24 and 33

Rev 24	Rev 33
Line 2613...	Line 2613...

`MCycle[1] :`	`MCycle[1] :`
`begin`	`begin`
`Set_BusB_To = 4'b0110;`	`Set_BusB_To = 4'b0110;`
`Set_Addr_To = aBC;`	`Set_Addr_To = aBC;`
	`if (IR[3] == 1'b0 )`
	`begin`
	`IncDec_16 = 4'b0110;`
	`end`
	`else`
	`begin`
	`IncDec_16 = 4'b1110;`
	`end`
`end`	`end`

`MCycle[2] :`	`MCycle[2] :`
`begin`	`begin`
`if (IR[3] == 1'b0 )`	`if (IR[3] == 1'b0 )`
`begin`	`begin`
`IncDec_16 = 4'b0110;`	`IncDec_16 = 4'b0010;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`IncDec_16 = 4'b1110;`	`IncDec_16 = 4'b1010;`
`end`	`end`
`IORQ = 1'b1;`	`IORQ = 1'b1;`
`Write = 1'b1;`	`Write = 1'b1;`
`I_BTR = 1'b1;`	`I_BTR = 1'b1;`
`end // case: 3`	`end // case: 3`
Line 2712...	Line 2720...
`end // if (Mode < 2 )`	`end // if (Mode < 2 )`

`end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)`	`end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)`

`// synopsys dc_script_begin`	`// synopsys dc_script_begin`
`// set_attribute current_design "revision" "$Id: tv80_mcode.v,v 1.4 2004-10-05 08:09:43 ghutchis Exp $" -type string -quiet`	`// set_attribute current_design "revision" "$Id: tv80_mcode.v,v 1.5 2004-11-03 00:14:26 ghutchis Exp $" -type string -quiet`
`// synopsys dc_script_end`	`// synopsys dc_script_end`
`endmodule // T80_MCode`	`endmodule // T80_MCode`

`No newline at end of file`	`No newline at end of file`