OpenCores
URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk/] [rtl/] [core/] [tv80_mcode.v] - Diff between revs 84 and 90

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 84 Rev 90
Line 160... Line 160...
  //    constant aBC    : std_logic_vector[2:0] = 3'b100;
  //    constant aBC    : std_logic_vector[2:0] = 3'b100;
  //    constant aDE    : std_logic_vector[2:0] = 3'b101;
  //    constant aDE    : std_logic_vector[2:0] = 3'b101;
  //    constant aZI    : std_logic_vector[2:0] = 3'b110;
  //    constant aZI    : std_logic_vector[2:0] = 3'b110;
 
 
  function is_cc_true;
  function is_cc_true;
    input [7:0] F;
    input [7:0] FF;
    input [2:0] cc;
    input [2:0] cc;
    begin
    begin
      if (Mode == 3 )
      if (Mode == 3 )
        begin
        begin
          case (cc)
          case (cc)
            3'b000  : is_cc_true = F[7] == 1'b0; // NZ
            3'b000  : is_cc_true = FF[7] == 1'b0; // NZ
            3'b001  : is_cc_true = F[7] == 1'b1; // Z
            3'b001  : is_cc_true = FF[7] == 1'b1; // Z
            3'b010  : is_cc_true = F[4] == 1'b0; // NC
            3'b010  : is_cc_true = FF[4] == 1'b0; // NC
            3'b011  : is_cc_true = F[4] == 1'b1; // C
            3'b011  : is_cc_true = FF[4] == 1'b1; // C
            3'b100  : is_cc_true = 0;
            3'b100  : is_cc_true = 0;
            3'b101  : is_cc_true = 0;
            3'b101  : is_cc_true = 0;
            3'b110  : is_cc_true = 0;
            3'b110  : is_cc_true = 0;
            3'b111  : is_cc_true = 0;
            3'b111  : is_cc_true = 0;
          endcase
          endcase
        end
        end
      else
      else
        begin
        begin
          case (cc)
          case (cc)
            3'b000  : is_cc_true = F[6] == 1'b0; // NZ
            3'b000  : is_cc_true = FF[6] == 1'b0; // NZ
            3'b001  : is_cc_true = F[6] == 1'b1; // Z
            3'b001  : is_cc_true = FF[6] == 1'b1; // Z
            3'b010  : is_cc_true = F[0] == 1'b0; // NC
            3'b010  : is_cc_true = FF[0] == 1'b0; // NC
            3'b011  : is_cc_true = F[0] == 1'b1; // C
            3'b011  : is_cc_true = FF[0] == 1'b1; // C
            3'b100  : is_cc_true = F[2] == 1'b0; // PO
            3'b100  : is_cc_true = FF[2] == 1'b0; // PO
            3'b101  : is_cc_true = F[2] == 1'b1; // PE
            3'b101  : is_cc_true = FF[2] == 1'b1; // PE
            3'b110  : is_cc_true = F[7] == 1'b0; // P
            3'b110  : is_cc_true = FF[7] == 1'b0; // P
            3'b111  : is_cc_true = F[7] == 1'b1; // M
            3'b111  : is_cc_true = FF[7] == 1'b1; // M
          endcase
          endcase
        end
        end
    end
    end
  endfunction // is_cc_true
  endfunction // is_cc_true
 
 
Line 268... Line 268...
            //
            //
            //  Unprefixed instructions
            //  Unprefixed instructions
            //
            //
            //----------------------------------------------------------------------------
            //----------------------------------------------------------------------------
 
 
            casex (IR)
            casez (IR)
              // 8 BIT LOAD GROUP
              // 8 BIT LOAD GROUP
              8'b01xxxxxx :
              8'b01zzzzzz :
                begin
                begin
                  if (IR[5:0] == 6'b110110)
                  if (IR[5:0] == 6'b110110)
                    Halt = 1'b1;
                    Halt = 1'b1;
                  else if (IR[2:0] == 3'b110)
                  else if (IR[2:0] == 3'b110)
                    begin
                    begin
Line 306... Line 306...
                      Set_BusB_To[2:0] = SSS;
                      Set_BusB_To[2:0] = SSS;
                      ExchangeRp = 1'b1;
                      ExchangeRp = 1'b1;
                      Set_BusA_To[2:0] = DDD;
                      Set_BusA_To[2:0] = DDD;
                      Read_To_Reg = 1'b1;
                      Read_To_Reg = 1'b1;
                    end // else: !if(IR[5:3] == 3'b110)
                    end // else: !if(IR[5:3] == 3'b110)
                end // case: 8'b01xxxxxx                                    
                end // case: 8'b01zzzzzz                                    
 
 
              8'b00xxx110 :
              8'b00zzz110 :
                begin
                begin
                  if (IR[5:3] == 3'b110)
                  if (IR[5:3] == 3'b110)
                    begin
                    begin
                      // LD (HL),n
                      // LD (HL),n
                      MCycles = 3'b011;
                      MCycles = 3'b011;
Line 621... Line 621...
                  // LD SP,HL
                  // LD SP,HL
                  TStates = 3'b110;
                  TStates = 3'b110;
                  LDSPHL = 1'b1;
                  LDSPHL = 1'b1;
                end
                end
 
 
              8'b11xx0101 :
              8'b11zz0101 :
                begin
                begin
                  // PUSH qq
                  // PUSH qq
                  MCycles = 3'b011;
                  MCycles = 3'b011;
                  case (1'b1) // MCycle                    
                  case (1'b1) // MCycle                    
                    MCycle[0] :
                    MCycle[0] :
Line 666... Line 666...
                      Write = 1'b1;
                      Write = 1'b1;
                    default :;
                    default :;
                  endcase // case(MCycle)
                  endcase // case(MCycle)
                end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101
                end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101
 
 
              8'b11xx0001 :
              8'b11zz0001 :
                begin
                begin
                  // POP qq
                  // POP qq
                  MCycles = 3'b011;
                  MCycles = 3'b011;
                  case (1'b1) // MCycle
                  case (1'b1) // MCycle
                    MCycle[0] :
                    MCycle[0] :
Line 837... Line 837...
                    end // if (Mode != 3 )
                    end // if (Mode != 3 )
                end // case: 8'b11100011
                end // case: 8'b11100011
 
 
 
 
              // 8 BIT ARITHMETIC AND LOGICAL GROUP
              // 8 BIT ARITHMETIC AND LOGICAL GROUP
              8'b10xxxxxx :
              8'b10zzzzzz :
                begin
                begin
                  if (IR[2:0] == 3'b110)
                  if (IR[2:0] == 3'b110)
                    begin
                    begin
                      // ADD A,(HL)
                      // ADD A,(HL)
                      // ADC A,(HL)
                      // ADC A,(HL)
Line 881... Line 881...
                      Read_To_Reg = 1'b1;
                      Read_To_Reg = 1'b1;
                      Save_ALU = 1'b1;
                      Save_ALU = 1'b1;
                    end // else: !if(IR[2:0] == 3'b110)                  
                    end // else: !if(IR[2:0] == 3'b110)                  
                end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
                end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
 
 
              8'b11xxx110 :
              8'b11zzz110 :
                begin
                begin
                  // ADD A,n
                  // ADD A,n
                  // ADC A,n
                  // ADC A,n
                  // SUB A,n
                  // SUB A,n
                  // SBC A,n
                  // SBC A,n
Line 902... Line 902...
                      Set_BusB_To[2:0] = SSS;
                      Set_BusB_To[2:0] = SSS;
                      Set_BusA_To[2:0] = 3'b111;
                      Set_BusA_To[2:0] = 3'b111;
                    end
                    end
                end
                end
 
 
              8'b00xxx100 :
              8'b00zzz100 :
                begin
                begin
                  if (IR[5:3] == 3'b110)
                  if (IR[5:3] == 3'b110)
                    begin
                    begin
                      // INC (HL)
                      // INC (HL)
                      MCycles = 3'b011;
                      MCycles = 3'b011;
Line 940... Line 940...
                      PreserveC = 1'b1;
                      PreserveC = 1'b1;
                      ALU_Op = 4'b0000;
                      ALU_Op = 4'b0000;
                    end
                    end
                end
                end
 
 
              8'b00xxx101 :
              8'b00zzz101 :
                begin
                begin
                  if (IR[5:3] == 3'b110)
                  if (IR[5:3] == 3'b110)
                    begin
                    begin
                      // DEC (HL)
                      // DEC (HL)
                      MCycles = 3'b011;
                      MCycles = 3'b011;
Line 1085... Line 1085...
              8'b11111011  :
              8'b11111011  :
                // EI
                // EI
                SetEI = 1'b1;
                SetEI = 1'b1;
 
 
              // 16 BIT ARITHMETIC GROUP
              // 16 BIT ARITHMETIC GROUP
              8'b00xx1001  :
              8'b00zz1001  :
                begin
                begin
                  // ADD HL,ss
                  // ADD HL,ss
                  MCycles = 3'b011;
                  MCycles = 3'b011;
                  case (1'b1) // MCycle
                  case (1'b1) // MCycle
                    MCycle[1] :
                    MCycle[1] :
Line 1132... Line 1132...
 
 
                    default :;
                    default :;
                  endcase // case(MCycle)
                  endcase // case(MCycle)
                end // case: 8'b00001001,8'b00011001,8'b00101001,8'b00111001              
                end // case: 8'b00001001,8'b00011001,8'b00101001,8'b00111001              
 
 
              8'b00xx0011 :
              8'b00zz0011 :
                begin
                begin
                  // INC ss
                  // INC ss
                  TStates = 3'b110;
                  TStates = 3'b110;
                  IncDec_16[3:2] = 2'b01;
                  IncDec_16[3:2] = 2'b01;
                  IncDec_16[1:0] = DPAIR;
                  IncDec_16[1:0] = DPAIR;
                end
                end
 
 
              8'b00xx1011 :
              8'b00zz1011 :
                begin
                begin
                  // DEC ss
                  // DEC ss
                  TStates = 3'b110;
                  TStates = 3'b110;
                  IncDec_16[3:2] = 2'b11;
                  IncDec_16[3:2] = 2'b11;
                  IncDec_16[1:0] = DPAIR;
                  IncDec_16[1:0] = DPAIR;
Line 1184... Line 1184...
                      Jump = 1'b1;
                      Jump = 1'b1;
                    end
                    end
 
 
                end // case: 8'b11000011
                end // case: 8'b11000011
 
 
              8'b11xxx010  :
              8'b11zzz010  :
                begin
                begin
                  if (IR[5] == 1'b1 && Mode == 3 )
                  if (IR[5] == 1'b1 && Mode == 3 )
                    begin
                    begin
                      case (IR[4:3])
                      case (IR[4:3])
                        2'b00  :
                        2'b00  :
Line 1316... Line 1316...
                      endcase
                      endcase
                    end // if (Mode != 2 )
                    end // if (Mode != 2 )
                end // case: 8'b00011000
                end // case: 8'b00011000
 
 
              // Conditional relative jumps (JR [C/NC/Z/NZ], e)
              // Conditional relative jumps (JR [C/NC/Z/NZ], e)
              8'b001xx000  :
              8'b001zz000  :
                begin
                begin
                  if (Mode != 2 )
                  if (Mode != 2 )
                    begin
                    begin
                      MCycles = 3'd3;
                      MCycles = 3'd3;
                      case (1'b1) // MCycle
                      case (1'b1) // MCycle
Line 1423... Line 1423...
                      end
                      end
                    default :;
                    default :;
                  endcase // case(MCycle)
                  endcase // case(MCycle)
                end // case: 8'b11001101
                end // case: 8'b11001101
 
 
              8'b11xxx100  :
              8'b11zzz100  :
                begin
                begin
                  if (IR[5] == 1'b0 || Mode != 3 )
                  if (IR[5] == 1'b0 || Mode != 3 )
                    begin
                    begin
                      // CALL cc,nn
                      // CALL cc,nn
                      MCycles = 3'b101;
                      MCycles = 3'b101;
Line 1770... Line 1770...
            //----------------------------------------------------------------------------
            //----------------------------------------------------------------------------
 
 
            Set_BusA_To[2:0] = IR[2:0];
            Set_BusA_To[2:0] = IR[2:0];
            Set_BusB_To[2:0] = IR[2:0];
            Set_BusB_To[2:0] = IR[2:0];
 
 
            casex (IR)
            casez (IR)
              8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,
              8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,
              8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010111,
              8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010111,
              8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001111,
              8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001111,
              8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011111,
              8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011111,
              8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100111,
              8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100111,
Line 1795... Line 1795...
                    Read_To_Reg = 1'b1;
                    Read_To_Reg = 1'b1;
                    Save_ALU = 1'b1;
                    Save_ALU = 1'b1;
                  end
                  end
                end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,...
                end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,...
 
 
              8'b00xxx110  :
              8'b00zzz110  :
                begin
                begin
                  // RLC (HL)
                  // RLC (HL)
                  // RL (HL)
                  // RL (HL)
                  // RRC (HL)
                  // RRC (HL)
                  // RR (HL)
                  // RR (HL)
Line 1950... Line 1950...
            //
            //
            //  ED prefixed instructions
            //  ED prefixed instructions
            //
            //
            //----------------------------------------------------------------------------
            //----------------------------------------------------------------------------
 
 
            casex (IR)
            casez (IR)
              /*
              /*
               * Undocumented NOP instructions commented out to reduce size of mcode
               * Undocumented NOP instructions commented out to reduce size of mcode
               *
               *
              8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000110,8'b00000111
              8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000110,8'b00000111
                ,8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001110,8'b00001111
                ,8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001110,8'b00001111
Line 2573... Line 2573...
 
 
                    default :;
                    default :;
                  endcase // case(MCycle)
                  endcase // case(MCycle)
                end // case: 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011
                end // case: 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011
 
 
 
              default : ;
 
 
            endcase // case(IR)                  
            endcase // case(IR)                  
          end // block: default_ed_block        
          end // block: default_ed_block        
      endcase // case(ISet)
      endcase // case(ISet)
 
 
      if (Mode == 1 )
      if (Mode == 1 )

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.