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[/] [tv80/] [trunk/] [rtl/] [core/] [tv80_reg.v] - Diff between revs 84 and 89
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| Rev 84 |
Rev 89 |
| Line 59... |
Line 59... |
assign DOBL = RegsL[AddrB];
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assign DOBL = RegsL[AddrB];
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assign DOCH = RegsH[AddrC];
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assign DOCH = RegsH[AddrC];
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assign DOCL = RegsL[AddrC];
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assign DOCL = RegsL[AddrC];
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// break out ram bits for waveform debug
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// break out ram bits for waveform debug
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// synopsys translate_off
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wire [7:0] B = RegsH[0];
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wire [7:0] C = RegsL[0];
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wire [7:0] D = RegsH[1];
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wire [7:0] E = RegsL[1];
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wire [7:0] H = RegsH[2];
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wire [7:0] H = RegsH[2];
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wire [7:0] L = RegsL[2];
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wire [7:0] L = RegsL[2];
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// synopsys dc_script_begin
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wire [15:0] IX = { RegsH[3], RegsL[3] };
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// set_attribute current_design "revision" "$Id: tv80_reg.v,v 1.1 2004-05-16 17:39:57 ghutchis Exp $" -type string -quiet
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wire [15:0] IY = { RegsH[7], RegsL[7] };
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// synopsys dc_script_end
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// synopsys translate_on
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endmodule
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endmodule
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