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[/] [tv80/] [trunk/] [rtl/] [core/] [tv80_reg.v] - Diff between revs 84 and 89

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Rev 84 Rev 89
Line 59... Line 59...
  assign DOBL = RegsL[AddrB];
  assign DOBL = RegsL[AddrB];
  assign DOCH = RegsH[AddrC];
  assign DOCH = RegsH[AddrC];
  assign DOCL = RegsL[AddrC];
  assign DOCL = RegsL[AddrC];
 
 
  // break out ram bits for waveform debug
  // break out ram bits for waveform debug
 
// synopsys translate_off
 
  wire [7:0] B = RegsH[0];
 
  wire [7:0] C = RegsL[0];
 
  wire [7:0] D = RegsH[1];
 
  wire [7:0] E = RegsL[1];
  wire [7:0] H = RegsH[2];
  wire [7:0] H = RegsH[2];
  wire [7:0] L = RegsL[2];
  wire [7:0] L = RegsL[2];
 
 
// synopsys dc_script_begin
  wire [15:0] IX = { RegsH[3], RegsL[3] };
// set_attribute current_design "revision" "$Id: tv80_reg.v,v 1.1 2004-05-16 17:39:57 ghutchis Exp $" -type string -quiet
  wire [15:0] IY = { RegsH[7], RegsL[7] };
// synopsys dc_script_end
// synopsys translate_on
 
 
endmodule
endmodule
 
 
 
 
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