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[/] [tv80/] [trunk/] [rtl/] [core/] [tv80n.v] - Diff between revs 84 and 100

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Rev 84 Rev 100
Line 25... Line 25...
// Negative-edge based wrapper allows memory wait_n signal to work
// Negative-edge based wrapper allows memory wait_n signal to work
// correctly without resorting to asynchronous logic.
// correctly without resorting to asynchronous logic.
 
 
module tv80n (/*AUTOARG*/
module tv80n (/*AUTOARG*/
  // Outputs
  // Outputs
  m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, do,
  m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
  // Inputs
  // Inputs
  reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
  reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
  );
  );
 
 
  parameter Mode = 0;    // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
  parameter Mode = 0;    // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
Line 51... Line 51...
  output        rfsh_n;
  output        rfsh_n;
  output        halt_n;
  output        halt_n;
  output        busak_n;
  output        busak_n;
  output [15:0] A;
  output [15:0] A;
  input [7:0]   di;
  input [7:0]   di;
  output [7:0]  do;
  output [7:0]  dout;
 
 
  reg           mreq_n;
  reg           mreq_n;
  reg           iorq_n;
  reg           iorq_n;
  reg           rd_n;
  reg           rd_n;
  reg           wr_n;
  reg           wr_n;
Line 94... Line 94...
     .IntE (),
     .IntE (),
     .stop (),
     .stop (),
     .A (A),
     .A (A),
     .dinst (di),
     .dinst (di),
     .di (di_reg),
     .di (di_reg),
     .do (do),
     .dout (dout),
     .mc (mcycle),
     .mc (mcycle),
     .ts (tstate),
     .ts (tstate),
     .intcycle_n (intcycle_n)
     .intcycle_n (intcycle_n)
     );
     );
 
 

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