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[/] [tv80/] [trunk/] [rtl/] [simple_gmii/] [simple_gmii_regs.v] - Diff between revs 84 and 90

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module simple_gmii_regs (
module simple_gmii_regs (
clk,reset,addr,wr_data,rd_data,doe,rd_n,wr_n,iorq_n,status_set,status_msk,control,control_clr,rx_len0,rx_len1,rx_data,rx_data_stb,tx_data,tx_data_stb,config,int_n);
clk,reset,addr,wr_data,rd_data,doe,rd_n,wr_n,iorq_n,status_set,status_msk,control,control_clr,rx_len0,rx_len1,rx_data,rx_data_stb,tx_data,tx_data_stb,cfg,int_n);
input clk;
input clk;
input reset;
input reset;
input [15:0] addr;
input [15:0] addr;
input [7:0] wr_data;
input [7:0] wr_data;
output [7:0] rd_data;
output [7:0] rd_data;
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input [7:0] rx_len1;
input [7:0] rx_len1;
input [7:0] rx_data;
input [7:0] rx_data;
output rx_data_stb;
output rx_data_stb;
output [7:0] tx_data;
output [7:0] tx_data;
output tx_data_stb;
output tx_data_stb;
output config;
output cfg;
output int_n;
output int_n;
reg [7:0] rd_data;
reg [7:0] rd_data;
reg block_select;
reg block_select;
reg doe;
reg doe;
reg status_rd_sel;
reg status_rd_sel;
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reg rx_data_stb;
reg rx_data_stb;
reg [7:0] tx_data;
reg [7:0] tx_data;
reg tx_data_rd_sel;
reg tx_data_rd_sel;
reg tx_data_wr_sel;
reg tx_data_wr_sel;
reg tx_data_stb;
reg tx_data_stb;
reg config;
reg cfg;
reg config_rd_sel;
reg cfg_rd_sel;
reg config_wr_sel;
reg cfg_wr_sel;
reg int_n;
reg int_n;
reg [7:0] int_vec;
reg [7:0] int_vec;
always @*
always @*
  begin
  begin
    block_select = (addr[7:3] == 1) & !iorq_n;
    block_select = (addr[7:3] == 1) & !iorq_n;
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    rx_len0_rd_sel = block_select & (addr[2:0] == 3) & !rd_n;
    rx_len0_rd_sel = block_select & (addr[2:0] == 3) & !rd_n;
    rx_len1_rd_sel = block_select & (addr[2:0] == 4) & !rd_n;
    rx_len1_rd_sel = block_select & (addr[2:0] == 4) & !rd_n;
    rx_data_rd_sel = block_select & (addr[2:0] == 5) & !rd_n;
    rx_data_rd_sel = block_select & (addr[2:0] == 5) & !rd_n;
    tx_data_rd_sel = block_select & (addr[2:0] == 6) & !rd_n;
    tx_data_rd_sel = block_select & (addr[2:0] == 6) & !rd_n;
    tx_data_wr_sel = block_select & (addr[2:0] == 6) & !wr_n;
    tx_data_wr_sel = block_select & (addr[2:0] == 6) & !wr_n;
    config_rd_sel = block_select & (addr[2:0] == 7) & !rd_n;
    cfg_rd_sel = block_select & (addr[2:0] == 7) & !rd_n;
    config_wr_sel = block_select & (addr[2:0] == 7) & !wr_n;
    cfg_wr_sel = block_select & (addr[2:0] == 7) & !wr_n;
  end
  end
always @*
always @*
  begin
  begin
    case (1'b1)
    case (1'b1)
      status_int : int_vec = 207;
      status_int : int_vec = 207;
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      control_rd_sel : rd_data = control;
      control_rd_sel : rd_data = control;
      rx_len0_rd_sel : rd_data = rx_len0;
      rx_len0_rd_sel : rd_data = rx_len0;
      rx_len1_rd_sel : rd_data = rx_len1;
      rx_len1_rd_sel : rd_data = rx_len1;
      rx_data_rd_sel : rd_data = rx_data;
      rx_data_rd_sel : rd_data = rx_data;
      tx_data_rd_sel : rd_data = tx_data;
      tx_data_rd_sel : rd_data = tx_data;
      config_rd_sel : rd_data = config;
      cfg_rd_sel : rd_data = cfg;
      default : rd_data = int_vec;
      default : rd_data = int_vec;
    endcase
    endcase
    doe = status_rd_sel | status_msk_rd_sel | control_rd_sel | rx_len0_rd_sel | rx_len1_rd_sel | rx_data_rd_sel | tx_data_rd_sel | config_rd_sel;
    doe = status_rd_sel | status_msk_rd_sel | control_rd_sel | rx_len0_rd_sel | rx_len1_rd_sel | rx_data_rd_sel | tx_data_rd_sel | cfg_rd_sel;
  end
  end
always @*
always @*
  begin
  begin
    int_n = ~(status_int);
    int_n = ~(status_int);
  end
  end
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    else if (tx_data_wr_sel) tx_data <= wr_data;
    else if (tx_data_wr_sel) tx_data <= wr_data;
    if (reset) tx_data_stb <= 0;
    if (reset) tx_data_stb <= 0;
    else if (tx_data_wr_sel) tx_data_stb <= 1;
    else if (tx_data_wr_sel) tx_data_stb <= 1;
    else tx_data_stb <= 0;
    else tx_data_stb <= 0;
  end
  end
// register: config
// register: cfg
always @(posedge clk)
always @(posedge clk)
  begin
  begin
    if (reset) config <= 0;
    if (reset) cfg <= 0;
    else if (config_wr_sel) config <= wr_data;
    else if (cfg_wr_sel) cfg <= wr_data;
  end
  end
endmodule
endmodule
 
 
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