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module simple_gmii_regs (
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module simple_gmii_regs (
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clk,reset,addr,wr_data,rd_data,doe,rd_n,wr_n,iorq_n,status_set,status_msk,control,control_clr,rx_len0,rx_len1,rx_data,rx_data_stb,tx_data,tx_data_stb,config,int_n);
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clk,reset,addr,wr_data,rd_data,doe,rd_n,wr_n,iorq_n,status_set,status_msk,control,control_clr,rx_len0,rx_len1,rx_data,rx_data_stb,tx_data,tx_data_stb,cfg,int_n);
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input clk;
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input clk;
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input reset;
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input reset;
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input [15:0] addr;
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input [15:0] addr;
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input [7:0] wr_data;
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input [7:0] wr_data;
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output [7:0] rd_data;
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output [7:0] rd_data;
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input [7:0] rx_len1;
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input [7:0] rx_len1;
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input [7:0] rx_data;
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input [7:0] rx_data;
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output rx_data_stb;
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output rx_data_stb;
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output [7:0] tx_data;
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output [7:0] tx_data;
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output tx_data_stb;
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output tx_data_stb;
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output config;
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output cfg;
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output int_n;
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output int_n;
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reg [7:0] rd_data;
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reg [7:0] rd_data;
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reg block_select;
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reg block_select;
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reg doe;
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reg doe;
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reg status_rd_sel;
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reg status_rd_sel;
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reg rx_data_stb;
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reg rx_data_stb;
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reg [7:0] tx_data;
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reg [7:0] tx_data;
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reg tx_data_rd_sel;
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reg tx_data_rd_sel;
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reg tx_data_wr_sel;
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reg tx_data_wr_sel;
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reg tx_data_stb;
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reg tx_data_stb;
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reg config;
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reg cfg;
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reg config_rd_sel;
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reg cfg_rd_sel;
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reg config_wr_sel;
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reg cfg_wr_sel;
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reg int_n;
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reg int_n;
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reg [7:0] int_vec;
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reg [7:0] int_vec;
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always @*
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always @*
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begin
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begin
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block_select = (addr[7:3] == 1) & !iorq_n;
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block_select = (addr[7:3] == 1) & !iorq_n;
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rx_len0_rd_sel = block_select & (addr[2:0] == 3) & !rd_n;
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rx_len0_rd_sel = block_select & (addr[2:0] == 3) & !rd_n;
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rx_len1_rd_sel = block_select & (addr[2:0] == 4) & !rd_n;
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rx_len1_rd_sel = block_select & (addr[2:0] == 4) & !rd_n;
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rx_data_rd_sel = block_select & (addr[2:0] == 5) & !rd_n;
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rx_data_rd_sel = block_select & (addr[2:0] == 5) & !rd_n;
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tx_data_rd_sel = block_select & (addr[2:0] == 6) & !rd_n;
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tx_data_rd_sel = block_select & (addr[2:0] == 6) & !rd_n;
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tx_data_wr_sel = block_select & (addr[2:0] == 6) & !wr_n;
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tx_data_wr_sel = block_select & (addr[2:0] == 6) & !wr_n;
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config_rd_sel = block_select & (addr[2:0] == 7) & !rd_n;
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cfg_rd_sel = block_select & (addr[2:0] == 7) & !rd_n;
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config_wr_sel = block_select & (addr[2:0] == 7) & !wr_n;
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cfg_wr_sel = block_select & (addr[2:0] == 7) & !wr_n;
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end
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end
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always @*
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always @*
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begin
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begin
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case (1'b1)
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case (1'b1)
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status_int : int_vec = 207;
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status_int : int_vec = 207;
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control_rd_sel : rd_data = control;
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control_rd_sel : rd_data = control;
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rx_len0_rd_sel : rd_data = rx_len0;
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rx_len0_rd_sel : rd_data = rx_len0;
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rx_len1_rd_sel : rd_data = rx_len1;
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rx_len1_rd_sel : rd_data = rx_len1;
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rx_data_rd_sel : rd_data = rx_data;
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rx_data_rd_sel : rd_data = rx_data;
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tx_data_rd_sel : rd_data = tx_data;
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tx_data_rd_sel : rd_data = tx_data;
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config_rd_sel : rd_data = config;
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cfg_rd_sel : rd_data = cfg;
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default : rd_data = int_vec;
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default : rd_data = int_vec;
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endcase
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endcase
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doe = status_rd_sel | status_msk_rd_sel | control_rd_sel | rx_len0_rd_sel | rx_len1_rd_sel | rx_data_rd_sel | tx_data_rd_sel | config_rd_sel;
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doe = status_rd_sel | status_msk_rd_sel | control_rd_sel | rx_len0_rd_sel | rx_len1_rd_sel | rx_data_rd_sel | tx_data_rd_sel | cfg_rd_sel;
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end
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end
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always @*
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always @*
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begin
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begin
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int_n = ~(status_int);
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int_n = ~(status_int);
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end
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end
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else if (tx_data_wr_sel) tx_data <= wr_data;
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else if (tx_data_wr_sel) tx_data <= wr_data;
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if (reset) tx_data_stb <= 0;
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if (reset) tx_data_stb <= 0;
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else if (tx_data_wr_sel) tx_data_stb <= 1;
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else if (tx_data_wr_sel) tx_data_stb <= 1;
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else tx_data_stb <= 0;
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else tx_data_stb <= 0;
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end
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end
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// register: config
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// register: cfg
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (reset) config <= 0;
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if (reset) cfg <= 0;
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else if (config_wr_sel) config <= wr_data;
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else if (cfg_wr_sel) cfg <= wr_data;
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end
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end
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endmodule
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endmodule
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