URL
https://opencores.org/ocsvn/tv80/tv80/trunk
[/] [tv80/] [trunk/] [rtl/] [simple_gmii/] [simple_gmii_top.v] - Diff between revs 84 and 90
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 84 |
Rev 90 |
| Line 28... |
Line 28... |
clk, reset, iorq_n, rd_n, addr, wr_data, wr_n, rx_clk, rx_data,
|
clk, reset, iorq_n, rd_n, addr, wr_data, wr_n, rx_clk, rx_data,
|
rx_dv, rx_er, tx_clk
|
rx_dv, rx_er, tx_clk
|
);
|
);
|
|
|
parameter txbuf_sz = 512, rxbuf_sz = 512;
|
parameter txbuf_sz = 512, rxbuf_sz = 512;
|
parameter wr_ptr_sz = 10;
|
parameter wr_ptr_sz = 9;
|
|
|
input clk; // To core0 of simple_gmii_core.v, ...
|
input clk; // To core0 of simple_gmii_core.v, ...
|
input reset; // To core0 of simple_gmii_core.v, ...
|
input reset; // To core0 of simple_gmii_core.v, ...
|
|
|
// TV80 Controls
|
// TV80 Controls
|
| Line 146... |
Line 146... |
.status_msk (),
|
.status_msk (),
|
.control (start_transmit),
|
.control (start_transmit),
|
.rx_data_stb (rx_rd_stb),
|
.rx_data_stb (rx_rd_stb),
|
.tx_data (tx_wr_data),
|
.tx_data (tx_wr_data),
|
.tx_data_stb (tx_wr_stb),
|
.tx_data_stb (tx_wr_stb),
|
.config (en_preamble),
|
.cfg (en_preamble),
|
.int_n (int_n),
|
.int_n (int_n),
|
// Inputs
|
// Inputs
|
.clk (clk),
|
.clk (clk),
|
.reset (reset),
|
.reset (reset),
|
.addr (addr[15:0]),
|
.addr (addr[15:0]),
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.