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[/] [tv80/] [trunk/] [rtl/] [uart/] [T16450.v] - Diff between revs 84 and 90

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Rev 84 Rev 90
Line 188... Line 188...
      MSR_In[3] <= #1 dcd_n;
      MSR_In[3] <= #1 dcd_n;
    end
    end
 
 
  always @*
  always @*
    begin
    begin
      IIR[7:3] <= #1 5'b00000;
      IIR[7:3] = #1 5'b00000;
      if (IER[2] && (LSR[4:1] != 4'b0000))
      if (IER[2] && (LSR[4:1] != 4'b0000))
        IIR[2:0] <= #1 3'b110;
        IIR[2:0] = #1 3'b110;
      else if (IER[0] && LSR[0])
      else if (IER[0] && LSR[0])
        IIR[2:0] <= #1 3'b100;
        IIR[2:0] = #1 3'b100;
      else if (IER[1] && LSR[5])
      else if (IER[1] && LSR[5])
        IIR[2:0] <= #1 3'b010;
        IIR[2:0] = #1 3'b010;
      else if (IER[3] && ((!MCR[4] && (MSR[3:0] != 0)) || (MCR[4] && (MCR[3:0] != 0))))
      else if (IER[3] && ((!MCR[4] && (MSR[3:0] != 0)) || (MCR[4] && (MCR[3:0] != 0))))
        IIR[2:0] <= #1 3'b000;
        IIR[2:0] = #1 3'b000;
      else
      else
        IIR[2:0] <= #1 3'b001;
        IIR[2:0] = #1 3'b001;
    end
    end
 
 
  // Baud x 16 clock generator
  // Baud x 16 clock generator
  always @ (posedge clk)
  always @ (posedge clk)
    begin : clk_gen
    begin : clk_gen
Line 282... Line 282...
              LSR[2] <= #1 1'b0;   // PE
              LSR[2] <= #1 1'b0;   // PE
              LSR[1] <= #1 1'b0;   // OE
              LSR[1] <= #1 1'b0;   // OE
            end
            end
          if (rclk)
          if (rclk)
            begin
            begin
              if (!RX_Bit_Cnt && (RX_Filtered || (Bit_Phase == 4'b0111)))
              if ((RX_Bit_Cnt == 0) && (RX_Filtered || (Bit_Phase == 4'b0111)))
                begin
                begin
                  Bit_Phase <= #1 4'b0000;
                  Bit_Phase <= #1 4'b0000;
                end
                end
              else
              else
                begin
                begin
Line 305... Line 305...
                  if (Brk_Cnt == 4'b1100)
                  if (Brk_Cnt == 4'b1100)
                    begin
                    begin
                      LSR[4] <= #1 1'b1;     // BI
                      LSR[4] <= #1 1'b1;     // BI
                    end
                    end
                end
                end
              if (!RX_Bit_Cnt )
              if (RX_Bit_Cnt == 0)
                begin
                begin
                  if (Bit_Phase == 4'b0111)
                  if (Bit_Phase == 4'b0111)
                    begin
                    begin
                      RX_Bit_Cnt <= #1 RX_Bit_Cnt + 1;
                      RX_Bit_Cnt <= #1 RX_Bit_Cnt + 1;
                      RX_Parity <= #1 ! LCR[4];    // EPS
                      RX_Parity <= #1 ! LCR[4];    // EPS

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