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[/] [tv80/] [trunk/] [rtl/] [uart/] [T16450.v] - Diff between revs 84 and 90
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| Rev 84 |
Rev 90 |
| Line 188... |
Line 188... |
MSR_In[3] <= #1 dcd_n;
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MSR_In[3] <= #1 dcd_n;
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end
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end
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always @*
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always @*
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begin
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begin
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IIR[7:3] <= #1 5'b00000;
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IIR[7:3] = #1 5'b00000;
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if (IER[2] && (LSR[4:1] != 4'b0000))
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if (IER[2] && (LSR[4:1] != 4'b0000))
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IIR[2:0] <= #1 3'b110;
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IIR[2:0] = #1 3'b110;
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else if (IER[0] && LSR[0])
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else if (IER[0] && LSR[0])
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IIR[2:0] <= #1 3'b100;
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IIR[2:0] = #1 3'b100;
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else if (IER[1] && LSR[5])
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else if (IER[1] && LSR[5])
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IIR[2:0] <= #1 3'b010;
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IIR[2:0] = #1 3'b010;
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else if (IER[3] && ((!MCR[4] && (MSR[3:0] != 0)) || (MCR[4] && (MCR[3:0] != 0))))
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else if (IER[3] && ((!MCR[4] && (MSR[3:0] != 0)) || (MCR[4] && (MCR[3:0] != 0))))
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IIR[2:0] <= #1 3'b000;
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IIR[2:0] = #1 3'b000;
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else
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else
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IIR[2:0] <= #1 3'b001;
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IIR[2:0] = #1 3'b001;
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end
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end
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// Baud x 16 clock generator
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// Baud x 16 clock generator
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always @ (posedge clk)
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always @ (posedge clk)
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begin : clk_gen
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begin : clk_gen
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| Line 282... |
Line 282... |
LSR[2] <= #1 1'b0; // PE
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LSR[2] <= #1 1'b0; // PE
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LSR[1] <= #1 1'b0; // OE
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LSR[1] <= #1 1'b0; // OE
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end
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end
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if (rclk)
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if (rclk)
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begin
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begin
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if (!RX_Bit_Cnt && (RX_Filtered || (Bit_Phase == 4'b0111)))
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if ((RX_Bit_Cnt == 0) && (RX_Filtered || (Bit_Phase == 4'b0111)))
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begin
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begin
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Bit_Phase <= #1 4'b0000;
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Bit_Phase <= #1 4'b0000;
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end
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end
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else
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else
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begin
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begin
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| Line 305... |
Line 305... |
if (Brk_Cnt == 4'b1100)
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if (Brk_Cnt == 4'b1100)
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begin
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begin
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LSR[4] <= #1 1'b1; // BI
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LSR[4] <= #1 1'b1; // BI
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end
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end
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end
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end
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if (!RX_Bit_Cnt )
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if (RX_Bit_Cnt == 0)
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begin
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begin
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if (Bit_Phase == 4'b0111)
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if (Bit_Phase == 4'b0111)
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begin
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begin
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RX_Bit_Cnt <= #1 RX_Bit_Cnt + 1;
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RX_Bit_Cnt <= #1 RX_Bit_Cnt + 1;
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RX_Parity <= #1 ! LCR[4]; // EPS
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RX_Parity <= #1 ! LCR[4]; // EPS
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