| Line 72... |
Line 72... |
self.name = ''
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self.name = ''
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self.local_width = 1
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self.local_width = 1
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self.registers = []
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self.registers = []
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self.ports = [port ('input', 'clk'), port('input','reset')]
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self.ports = [port ('input', 'clk'), port('input','reset')]
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self.nets = []
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self.nets = []
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self.interrupts = 0
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if (mem_mapped):
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if (mem_mapped):
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self.req_pin = 'mreq_n'
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self.req_pin = 'mreq_n'
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else:
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else:
|
self.req_pin = 'iorq_n'
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self.req_pin = 'iorq_n'
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self.tv80_intf()
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self.tv80_intf()
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| Line 86... |
Line 87... |
self.ports.append (port ('output', 'rd_data', self.data_size))
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self.ports.append (port ('output', 'rd_data', self.data_size))
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self.ports.append (port ('output', 'doe'))
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self.ports.append (port ('output', 'doe'))
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self.ports.append (port ('input','rd_n'))
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self.ports.append (port ('input','rd_n'))
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self.ports.append (port ('input', 'wr_n'))
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self.ports.append (port ('input', 'wr_n'))
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self.ports.append (port ('input', self.req_pin))
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self.ports.append (port ('input', self.req_pin))
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self.nets.append (net('reg','rd_data',self.data_size))
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self.nets.append (net('reg','block_select'))
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self.nets.append (net('reg','doe'))
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|
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# create a hook for post-processing to be done after all data has been
|
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# added to the object.
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def post (self):
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self.int_ports()
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|
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# create port for interrupt pin, as well as port for data output enable
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# when interrupt is asserted.
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# This block should be called after all register data has been read.
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def int_ports (self):
|
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self.ports.append (port ('output','int_n'))
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self.nets.append (net ('reg','int_n'))
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|
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def int_logic (self):
|
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statements = []
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int_nets = []
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for r in self.registers:
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if r.interrupt: int_nets.append (r.name + "_int")
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statements.append ("int_n = ~(" + string.join (int_nets, ' | ') + ");")
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return comb_block (statements)
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def global_logic (self):
|
def global_logic (self):
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# create select pin for this block
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# create select pin for this block
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self.nets.append (net('reg','block_select'))
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statements = ["block_select = (addr[%d:%d] == %d) & !%s;" % (self.addr_size-1,self.local_width,self.base_addr >> self.local_width, self.req_pin)]
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statements = ["block_select = (addr[%d:%d] == %d) & !%s;" % (self.addr_size-1,self.local_width,self.base_addr >> self.local_width, self.req_pin)]
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|
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# create read and write selects for each register
|
# create read and write selects for each register
|
for r in self.registers:
|
for r in self.registers:
|
s = "%s_rd_sel = block_select & (addr[%d:%d] == %d) & !rd_n;" % (r.name,self.local_width-1,0,r.offset)
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slogic = "block_select & (addr[%d:%d] == %d) & !rd_n" % (self.local_width-1,0,r.offset)
|
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if r.interrupt:
|
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slogic = "%s_int | (%s)" % (r.name, slogic)
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s = "%s_rd_sel = %s;" % (r.name,slogic)
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statements.append (s)
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statements.append (s)
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if r.write_cap():
|
if r.write_cap():
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s = "%s_wr_sel = block_select & (addr[%d:%d] == %d) & !wr_n;" % (r.name,self.local_width-1,0,r.offset)
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s = "%s_wr_sel = block_select & (addr[%d:%d] == %d) & !wr_n;" % (r.name,self.local_width-1,0,r.offset)
|
statements.append (s)
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statements.append (s)
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|
|
return comb_block (statements)
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return comb_block (statements)
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|
|
def read_mux (self):
|
def read_mux (self):
|
s = ''
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s = ''
|
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sments = []
|
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rd_sel_list = []
|
|
# Old code for simple tri-state interface
|
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#for r in self.registers:
|
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# s += "assign rd_data = (%s_rd_sel) ? %s : %d'bz;\n" % (r.name, r.name, self.data_size)
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|
|
|
sments.append ("case (1'b1)")
|
for r in self.registers:
|
for r in self.registers:
|
s += "assign rd_data = (%s_rd_sel) ? %s : %d'bz;\n" % (r.name, r.name, self.data_size)
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sments.append (" %s_rd_sel : rd_data = %s;" % (r.name, r.name))
|
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rd_sel_list.append (r.name + "_rd_sel")
|
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sments.append (" default : rd_data = %d'bx;" % self.data_size)
|
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sments.append ("endcase")
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|
|
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sments.append ("doe = %s;" % string.join (rd_sel_list, ' | '))
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|
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return s
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return comb_block (sments)
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|
|
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def verilog (self):
|
def verilog (self):
|
|
self.post()
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|
|
result = 'module ' + self.name + ' (\n'
|
result = 'module ' + self.name + ' (\n'
|
result += string.join (map (lambda x: x.name, self.ports), ',')
|
result += string.join (map (lambda x: x.name, self.ports), ',')
|
result += ');\n'
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result += ');\n'
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|
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# print port list
|
# print port list
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| Line 126... |
Line 166... |
result += n.declaration() + '\n'
|
result += n.declaration() + '\n'
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|
|
# create global logic
|
# create global logic
|
result += self.global_logic()
|
result += self.global_logic()
|
result += self.read_mux()
|
result += self.read_mux()
|
|
if (self.interrupts > 0): result += self.int_logic()
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|
|
# print function blocks
|
# print function blocks
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for r in self.registers:
|
for r in self.registers:
|
result += r.verilog_body()
|
result += r.verilog_body()
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|
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result += 'endmodule;\n'
|
result += 'endmodule\n'
|
return result
|
return result
|
|
|
def add_register (self, name, type, width):
|
def add_register (self, type, params):
|
|
#def add_register (self, name, type, width):
|
if (type == 'status'):
|
if (type == 'status'):
|
self.add (status_reg (name,width))
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self.add (status_reg (params['name'],params['width']))
|
elif (type == 'config'):
|
elif (type == 'config'):
|
self.add (config_reg (name,width))
|
self.add (config_reg (params['name'],params['width'],params['default']))
|
|
elif (type == 'int_fixed'):
|
|
r2 = config_reg (params['name'] + "_msk",params['width'],params['default'])
|
|
r1 = int_fixed_reg (params['name'],r2,params['width'])
|
|
self.add (r1)
|
|
self.add (r2)
|
|
self.interrupts += 1
|
|
elif (type == 'soft_set'):
|
|
self.add (soft_set_reg(params['name'],params['width'],params['default']))
|
|
elif (type == 'read_stb'):
|
|
self.add (read_stb_reg (params['name'],params['width']))
|
|
elif (type == 'write_stb'):
|
|
self.add (config_reg (params['name'],params['width'],params['default']))
|
else:
|
else:
|
print "Unknown register type",type
|
print "Unknown register type",type
|
|
|
def add (self, reg):
|
def add (self, reg):
|
self.registers.append (reg)
|
self.registers.append (reg)
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| Line 157... |
Line 211... |
class basic_register:
|
class basic_register:
|
def __init__ (self, name='', width=0):
|
def __init__ (self, name='', width=0):
|
self.offset = 0
|
self.offset = 0
|
self.width = width
|
self.width = width
|
self.name = name
|
self.name = name
|
|
self.interrupt = 0
|
|
|
def verilog_body (self):
|
def verilog_body (self):
|
pass
|
pass
|
|
|
def io (self):
|
def io (self):
|
| Line 170... |
Line 225... |
return []
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return []
|
|
|
def write_cap (self):
|
def write_cap (self):
|
return 0
|
return 0
|
|
|
|
def id_comment (self):
|
|
return "// register: %s\n" % self.name
|
|
|
class status_reg (basic_register):
|
class status_reg (basic_register):
|
def __init__ (self, name='', width=0):
|
def __init__ (self, name='', width=0):
|
basic_register.__init__(self, name, width)
|
basic_register.__init__(self, name, width)
|
|
|
def verilog_body (self):
|
def verilog_body (self):
|
pass
|
return ''
|
|
|
def io (self):
|
def io (self):
|
return [('input',self.width, self.name)]
|
return [port('input', self.name, self.width)]
|
|
|
def nets (self):
|
def nets (self):
|
return [ net('reg', name + '_rd_sel')]
|
return [ net('reg', self.name + '_rd_sel')]
|
|
|
class config_reg (basic_register):
|
class config_reg (basic_register):
|
def __init__ (self, name='', width=0):
|
def __init__ (self, name='', width=0, default=0):
|
basic_register.__init__(self, name, width)
|
basic_register.__init__(self, name, width)
|
self.default = 0
|
self.default = default
|
|
|
def verilog_body (self):
|
def verilog_body (self):
|
statements = ["if (reset) %s <= %d;" % (self.name, self.default),
|
statements = ["if (reset) %s <= %d;" % (self.name, self.default),
|
"else if %s_wr_sel %s <= %s;" % (self.name, self.name, 'wr_data')
|
"else if (%s_wr_sel) %s <= %s;" % (self.name, self.name, 'wr_data')
|
]
|
]
|
return seq_block ('clk', statements)
|
return self.id_comment() + seq_block ('clk', statements)
|
|
|
def io (self):
|
def io (self):
|
return [ port('output',self.name, self.width) ]
|
return [ port('output',self.name, self.width) ]
|
|
|
def nets (self):
|
def nets (self):
|
return [ net('reg', self.name + '_rd_sel'), net('reg', self.name + '_wr_sel')]
|
return [ net('reg', self.name, self.width),
|
|
net('reg', self.name + '_rd_sel'),
|
|
net('reg', self.name + '_wr_sel')]
|
|
|
|
def write_cap (self):
|
|
return 1
|
|
|
|
class int_fixed_reg (basic_register):
|
|
def __init__ (self, name, mask_reg, width=0):
|
|
basic_register.__init__(self, name, width)
|
|
self.mask_reg = mask_reg
|
|
self.interrupt = 1
|
|
|
|
def verilog_body (self):
|
|
statements = ["if (reset) %s <= %d;" % (self.name, 0),
|
|
"else %s <= (%s_set | %s) & ~( {%d{%s}} & %s);" %
|
|
(self.name, self.name, self.name, self.width, self.name + '_wr_sel', 'wr_data'),
|
|
"if (reset) %s_int <= 0;" % self.name,
|
|
"else %s_int <= |(%s & ~%s);" % (self.name, self.name, self.mask_reg.name)
|
|
]
|
|
return self.id_comment() + seq_block ('clk', statements)
|
|
|
|
def io (self):
|
|
return [ port('input',self.name+"_set", self.width) ]
|
|
|
|
def nets (self):
|
|
return [ net('reg', self.name + '_rd_sel'),
|
|
net('reg', self.name, self.width),
|
|
net('reg', self.name + '_wr_sel'),
|
|
net('reg', self.name + '_int')]
|
|
|
def write_cap (self):
|
def write_cap (self):
|
return 1
|
return 1
|
|
|
|
class soft_set_reg (basic_register):
|
|
def __init__ (self, name='', width=0, default=0):
|
|
basic_register.__init__(self, name, width)
|
|
self.default = default
|
|
|
|
def verilog_body (self):
|
|
statements = ["if (reset) %s <= %d;" % (self.name, self.default),
|
|
"else %s <= ( ({%d{%s}} & %s) | %s) & ~(%s);" %
|
|
(self.name, self.width, self.name+'_wr_sel', 'wr_data',
|
|
self.name, self.name + '_clr')
|
|
]
|
|
return self.id_comment() + seq_block ('clk', statements)
|
|
|
|
def io (self):
|
|
return [ port('output',self.name, self.width),
|
|
port ('input',self.name+"_clr", self.width)]
|
|
|
|
def nets (self):
|
|
return [ net('reg', self.name, self.width),
|
|
net('reg', self.name + '_rd_sel'),
|
|
net('reg', self.name + '_wr_sel')]
|
|
|
|
def write_cap (self):
|
|
return 1
|
|
|
|
class write_stb_reg (config_reg):
|
|
def __init__ (self, name='', width=0, default=0):
|
|
config_reg.__init__(self, name, width, default)
|
|
|
|
def verilog_body (self):
|
|
statements = ["if (reset) %s <= %d;" % (self.name, self.default),
|
|
"else if (%s_wr_sel) %s <= %s;" % (self.name, self.name, 'wr_data'),
|
|
"if (reset) %s_stb <= 0;" % (self.name),
|
|
"else if (%s_wr_sel) %s_stb <= 1;" % (self.name),
|
|
"else %s_stb <= 0;" % (self.name)
|
|
]
|
|
return seq_block ('clk', statements)
|
|
|
|
def io (self):
|
|
io_list = config_reg.io (self)
|
|
io_list.append ( port('output',self.name+"_stb") )
|
|
return io_list
|
|
|
|
def nets (self):
|
|
net_list = config_reg.nets (self)
|
|
net_list.append ( net('reg', self.name + "_stb") )
|
|
return net_list
|
|
|
|
class read_stb_reg (status_reg):
|
|
def __init__ (self, name='', width=0):
|
|
status_reg.__init__(self, name, width)
|
|
|
|
def verilog_body (self):
|
|
statements = [
|
|
"if (reset) %s_stb <= 0;" % (self.name),
|
|
"else if (%s_rd_sel) %s_stb <= 1;" % (self.name, self.name),
|
|
"else %s_stb <= 0;" % (self.name)
|
|
]
|
|
return self.id_comment() + seq_block ('clk', statements)
|
|
|
|
def io (self):
|
|
io_list = status_reg.io (self)
|
|
io_list.append (port('output',self.name+"_stb"))
|
|
return io_list
|
|
|
|
def nets (self):
|
|
net_list = status_reg.nets(self)
|
|
net_list.append (net('reg',self.name + '_stb'))
|
|
return net_list
|
|
|
No newline at end of file
|
No newline at end of file
|
