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https://opencores.org/ocsvn/tv80/tv80/trunk
[/] [tv80/] [trunk/] [tests/] [bintr.c] - Diff between revs 84 and 89
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| Rev 84 |
Rev 89 |
| Line 13... |
Line 13... |
*/
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*/
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unsigned char foo;
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unsigned char foo;
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volatile unsigned char test_pass;
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volatile unsigned char test_pass;
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static unsigned char triggers;
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static unsigned char triggers;
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int phase;
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char done;
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char nmi_trig;
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void nmi_isr (void)
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{
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nmi_trig++;
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switch (phase) {
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// nmi test
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case 1 :
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if (nmi_trig > 5) {
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phase += 1;
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nmi_trig = 0;
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//intr_cntdwn = 255;
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//intr_cntdwn = 0;
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intr_cntdwn = 32;
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nmi_cntdwn = 0;
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} else
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nmi_cntdwn = 32;
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break;
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// just trigger once, and disable interrupt
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case 3 :
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nmi_cntdwn = 0;
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nmi_trig_opcode = 0; // pop AF opcode
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break;
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}
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}
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void isr (void)
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void isr (void)
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{
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{
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int i;
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triggers++;
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triggers++;
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switch (phase) {
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// int test
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case 0 :
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if (triggers > 5) {
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if (triggers > 5) {
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test_pass = 1;
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phase += 1;
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intr_cntdwn = 255;
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triggers = 0;
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intr_cntdwn = 0;
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intr_cntdwn = 0;
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} else
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nmi_cntdwn = 64;
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} else {
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intr_cntdwn = 32;
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intr_cntdwn = 32;
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}
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break;
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// int / nmi interaction
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// in this phase set up interrupt call
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// which will be interrupted by an nmi
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case 2 :
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phase += 1;
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triggers = 0;
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nmi_trig = 0;
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intr_cntdwn = 20;
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nmi_trig_opcode = 0xF1; // pop AF opcode
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break;
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// wait for a while while servicing interrupt
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// nmi should interrupt us and increment nmi_trig
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// if test pass is true when we are done then exit
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case 3 :
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intr_cntdwn = 0;
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if (nmi_trig == 1)
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test_pass = 1;
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break;
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}
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}
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}
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int main ()
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int main ()
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{
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{
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int i;
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int i;
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unsigned char check;
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unsigned char check;
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test_pass = 0;
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test_pass = 0;
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triggers = 0;
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triggers = 0;
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nmi_trig = 0;
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phase = 0;
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// start interrupt countdown
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// start interrupt countdown
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intr_cntdwn = 64;
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intr_cntdwn = 64;
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set_timeout (50000);
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for (i=0; i<200; i++)
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for (i=0; i<1024; i++) {
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if (test_pass)
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break;
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check = sim_ctl_port;
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check = sim_ctl_port;
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}
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if (test_pass)
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if (test_pass)
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sim_ctl (SC_TEST_PASSED);
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sim_ctl (SC_TEST_PASSED);
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else
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else
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sim_ctl (SC_TEST_FAILED);
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sim_ctl (SC_TEST_FAILED);
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