URL
https://opencores.org/ocsvn/tv80/tv80/trunk
[/] [tv80/] [trunk/] [tests/] [bintr.c] - Diff between revs 84 and 89
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 84 |
Rev 89 |
| Line 13... |
Line 13... |
*/
|
*/
|
|
|
unsigned char foo;
|
unsigned char foo;
|
volatile unsigned char test_pass;
|
volatile unsigned char test_pass;
|
static unsigned char triggers;
|
static unsigned char triggers;
|
|
int phase;
|
|
char done;
|
|
char nmi_trig;
|
|
|
|
void nmi_isr (void)
|
|
{
|
|
nmi_trig++;
|
|
|
|
switch (phase) {
|
|
// nmi test
|
|
case 1 :
|
|
if (nmi_trig > 5) {
|
|
phase += 1;
|
|
nmi_trig = 0;
|
|
//intr_cntdwn = 255;
|
|
//intr_cntdwn = 0;
|
|
intr_cntdwn = 32;
|
|
nmi_cntdwn = 0;
|
|
} else
|
|
nmi_cntdwn = 32;
|
|
break;
|
|
|
|
// just trigger once, and disable interrupt
|
|
case 3 :
|
|
nmi_cntdwn = 0;
|
|
nmi_trig_opcode = 0; // pop AF opcode
|
|
break;
|
|
}
|
|
}
|
|
|
void isr (void)
|
void isr (void)
|
{
|
{
|
|
int i;
|
triggers++;
|
triggers++;
|
|
|
|
switch (phase) {
|
|
// int test
|
|
case 0 :
|
if (triggers > 5) {
|
if (triggers > 5) {
|
test_pass = 1;
|
phase += 1;
|
intr_cntdwn = 255;
|
triggers = 0;
|
intr_cntdwn = 0;
|
intr_cntdwn = 0;
|
} else
|
nmi_cntdwn = 64;
|
|
} else {
|
intr_cntdwn = 32;
|
intr_cntdwn = 32;
|
|
|
|
}
|
|
break;
|
|
|
|
|
|
// int / nmi interaction
|
|
// in this phase set up interrupt call
|
|
// which will be interrupted by an nmi
|
|
case 2 :
|
|
phase += 1;
|
|
triggers = 0;
|
|
nmi_trig = 0;
|
|
intr_cntdwn = 20;
|
|
nmi_trig_opcode = 0xF1; // pop AF opcode
|
|
|
|
break;
|
|
|
|
// wait for a while while servicing interrupt
|
|
// nmi should interrupt us and increment nmi_trig
|
|
// if test pass is true when we are done then exit
|
|
case 3 :
|
|
intr_cntdwn = 0;
|
|
if (nmi_trig == 1)
|
|
test_pass = 1;
|
|
break;
|
|
|
|
}
|
}
|
}
|
|
|
int main ()
|
int main ()
|
{
|
{
|
int i;
|
int i;
|
unsigned char check;
|
unsigned char check;
|
|
|
test_pass = 0;
|
test_pass = 0;
|
triggers = 0;
|
triggers = 0;
|
|
nmi_trig = 0;
|
|
|
|
phase = 0;
|
|
|
// start interrupt countdown
|
// start interrupt countdown
|
intr_cntdwn = 64;
|
intr_cntdwn = 64;
|
|
set_timeout (50000);
|
|
|
for (i=0; i<200; i++)
|
for (i=0; i<1024; i++) {
|
|
if (test_pass)
|
|
break;
|
check = sim_ctl_port;
|
check = sim_ctl_port;
|
|
}
|
|
|
if (test_pass)
|
if (test_pass)
|
sim_ctl (SC_TEST_PASSED);
|
sim_ctl (SC_TEST_PASSED);
|
else
|
else
|
sim_ctl (SC_TEST_FAILED);
|
sim_ctl (SC_TEST_FAILED);
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.