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//
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/**********************************************************************
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// File: fht_8x8_core.v
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* File : fht_8x8_core.v
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// Author: Ivan Rezki
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* Author: Ivan Rezki
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// Topic: RTL Core
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* email : irezki@gmail.com
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// 2-Dimensional Fast Hartley Transform
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* Topic : RTL Core
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//
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* 2-Dimensional Fast Hartley Transform
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*
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// TOP Level
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* Compilation Notes:
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// 2D FHT 64 points -> ... clk delay
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* 1).Memory
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//
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* - if you use Xilinx FPGA for prototyping
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// +------------------------+
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* compile this code along with
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// | |
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* USE_FPGA_SPSRAM definition and
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// --->| 2D FHT/64 Points |--->
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* XilinxCoreLib library,
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// | |
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* - otherwise compile this code
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// +------------------------+
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* along with USE_ASIC_SPSRAM
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// |<---- .. clk delay ---->|
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* 2).Multiplier
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//
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* - if you use Xilinx FPGA for prototyping
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* compile this code along with
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// Data is coming from somewhere (e.g. memory) with sclk one by one.
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* USE_FPGA_MULT definition
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// 1st step 1D FHT by rows:
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* - otherwise compile this code
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// - Shift Register for 8 points -> ... clk delay
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* along with USE_ASIC_MULT
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// - Alligner
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*
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// - Calculate 1D FHT for 8 points. -> ... clk delay
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* TOP Level
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// - FF is used on the each input of the butterfly
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* 2D FHT 64 points -> ... clk delay
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// - FF is used on the input of the multiplier
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*
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// 2nd Step:
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* +------------------------+
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// Matrix Transpose -> 64+1 clk delay
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* | |
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// - Collecting data until 1st buffer is full as 64 points.
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* --->| 2D FHT/64 Points |--->
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// - Read 64 points right away after 1st buffer is full.
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* | |
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// - At the same time 2nd buffer is ready to receive data.
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* +------------------------+
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// - Collecting data until 2nd buffer is full as 64 points.
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* |<---- .. clk delay ---->|
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// - Read 64 points right away after 2nd buffer is full.
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*
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// - At the same time 1st buffer is ready to receive data once again.
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*
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// - ...
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* Data is coming from somewhere (e.g. memory) with sclk one by one.
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// 3rd Step 1D FHT by columns.
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* 1st step 1D FHT by rows:
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// - Combine data to make 8 points in parallel. -> ... clk delay
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* - Shift Register for 8 points -> ... clk delay
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// - Calculate 1D FHT for 8 points. -> ... clk delay
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* - Alligner
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* - Calculate 1D FHT for 8 points. -> ... clk delay
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* - FF is used on the each input of the butterfly
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* - FF is used on the input of the multiplier
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* 2nd Step:
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* Matrix Transpose -> 64+1 clk delay
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* - Collecting data until 1st buffer is full as 64 points.
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* - Read 64 points right away after 1st buffer is full.
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* - At the same time 2nd buffer is ready to receive data.
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* - Collecting data until 2nd buffer is full as 64 points.
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* - Read 64 points right away after 2nd buffer is full.
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* - At the same time 1st buffer is ready to receive data once again.
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* - ...
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* 3rd Step 1D FHT by columns.
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* - Combine data to make 8 points in parallel. -> ... clk delay
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* - Calculate 1D FHT for 8 points. -> ... clk delay
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*
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* RIGHT TO USE: This code example, or any portion thereof, may be
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* used and distributed without restriction, provided that this entire
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* comment block is included with the example.
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*
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* DISCLAIMER: THIS CODE EXAMPLE IS PROVIDED "AS IS" WITHOUT WARRANTY
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* OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED
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* TO WARRANTIES OF MERCHANTABILITY, FITNESS OR CORRECTNESS. IN NO
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* EVENT SHALL THE AUTHOR OR AUTHORS BE LIABLE FOR ANY DAMAGES,
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* INCLUDING INCIDENTAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF THE
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* USE OF THIS CODE.
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**********************************************************************/
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// NOTES:
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// NOTES:
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// 1. Matrix Transposition maximum data width is 16 bits.
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// 1. Matrix Transposition maximum data width is 16 bits.
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// ----->>> Define Multiplier Type
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// ----->>> Define Multiplier Type
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//`define USE_ASIC_MULT
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`define USE_ASIC_MULT
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//`define USE_FPGA_MULT
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//`define USE_FPGA_MULT
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// ----->>> Define Memory Type
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// ----->>> Define Memory Type
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//`define USE_FPGA_SPSRAM
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//`define USE_FPGA_SPSRAM
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//`define USE_ASIC_SPSRAM
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`define USE_ASIC_SPSRAM
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module fht_8x8_core (
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module fht_8x8_core (
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rstn,
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rstn,
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sclk,
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sclk,
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);
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);
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// +++--->>> Matrix Transposition <<<---+++ \\
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// +++--->>> Matrix Transposition <<<---+++ \\
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wire mem_valid;
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wire mem_valid;
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wire [N+2:0] mem_data;
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wire [N+2:0] mem_data;
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//mtx_trps_8x8_spsram #(N+3) u2_mtx_ts (
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// .rstn (rstn),
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// .sclk (sclk),
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//
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// .inp_valid (fht_1d_valid),
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// .inp_data (fht_1d_data),
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//
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// .mem_mux_data (mem_data),
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// .mem_mux_valid (mem_valid)
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//);
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mtx_trps_8x8_dpsram #(N+3) u2_mtx_ts (
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mtx_trps_8x8_dpsram #(N+3) u2_mtx_ts (
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.rstn (rstn),
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.rstn (rstn),
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.sclk (sclk),
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.sclk (sclk),
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