| Line 4... |
Line 4... |
* email : irezki@gmail.com
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* email : irezki@gmail.com
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* Topic : RTL Core
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* Topic : RTL Core
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* 2-Dimensional Fast Hartley Transform
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* 2-Dimensional Fast Hartley Transform
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*
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*
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* Compilation Notes:
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* Compilation Notes:
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* 1).Memory
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* 1).Input Data
|
|
* - no min.negative value
|
|
* 2).Memory
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* - if you use Xilinx FPGA for prototyping
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* - if you use Xilinx FPGA for prototyping
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* compile this code along with
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* compile this code along with
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* USE_FPGA_SPSRAM definition and
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* USE_FPGA_SPSRAM definition and
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* XilinxCoreLib library,
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* XilinxCoreLib library,
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* - otherwise compile this code
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* - otherwise compile this code
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* along with USE_ASIC_SPSRAM
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* along with USE_ASIC_SPSRAM
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* 2).Multiplier
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* - max. bitwidth is 16bits
|
|
* 3).Multiplier
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* - if you use Xilinx FPGA for prototyping
|
* - if you use Xilinx FPGA for prototyping
|
* compile this code along with
|
* compile this code along with
|
* USE_FPGA_MULT definition
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* USE_FPGA_MULT definition
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* - otherwise compile this code
|
* - otherwise compile this code
|
* along with USE_ASIC_MULT
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* along with USE_ASIC_MULT
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*
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*
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* TOP Level
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* TOP Level
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* 2D FHT 64 points -> ... clk delay
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* 2D FHT 64 points -> ... clk delay
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*
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*
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* +------------------------+
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* +-------------------------+
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* | |
|
* | |
|
* --->| 2D FHT/64 Points |--->
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* --->| 2D FHT/8x8 Points |--->
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* | |
|
* | |
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* +------------------------+
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* +-------------------------+
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* |<---- .. clk delay ---->|
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* |<---- ... clk delay ---->|
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*
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*
|
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* Input Data : [N-1:0] signed
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* Output Data : [N+5:0] signed
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*
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*
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* Data is coming from somewhere (e.g. memory) with sclk one by one.
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* Data is coming from somewhere (e.g. memory) with sclk one by one.
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* 1st step 1D FHT by rows:
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* 1st step 1D FHT by rows:
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* - Shift Register for 8 points -> ... clk delay
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* - Shift Register for 8 points -> ... clk delay
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* - Alligner
|
* - Alligner
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| Line 61... |
Line 66... |
* EVENT SHALL THE AUTHOR OR AUTHORS BE LIABLE FOR ANY DAMAGES,
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* EVENT SHALL THE AUTHOR OR AUTHORS BE LIABLE FOR ANY DAMAGES,
|
* INCLUDING INCIDENTAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF THE
|
* INCLUDING INCIDENTAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF THE
|
* USE OF THIS CODE.
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* USE OF THIS CODE.
|
**********************************************************************/
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**********************************************************************/
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|
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// NOTES:
|
|
// 1. Matrix Transposition maximum data width is 16 bits.
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|
|
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// ----->>> Define Multiplier Type
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// ----->>> Define Multiplier Type
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`define USE_ASIC_MULT
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//`define USE_ASIC_MULT
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//`define USE_FPGA_MULT
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//`define USE_FPGA_MULT
|
|
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// ----->>> Define Memory Type
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// ----->>> Define Memory Type
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//`define USE_FPGA_SPSRAM
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//`define USE_FPGA_SPSRAM
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`define USE_ASIC_SPSRAM
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//`define USE_ASIC_SPSRAM
|
|
|
module fht_8x8_core (
|
module fht_8x8_core (
|
rstn,
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rstn,
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sclk,
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sclk,
|
|
|
