| Line 21... |
Line 21... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Revision list
|
-- Revision list
|
-- Version Author Date Changes
|
-- Version Author Date Changes
|
--
|
--
|
-- 0.1 Ovidiu Lupas 15 January 2000 New model
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-- 0.1 Ovidiu Lupas 15 January 2000 New model
|
-- ovilup@mail.dnttm.ro
|
-- 2.0 Ovidiu Lupas 17 April 2000 samples counter cleared for bit 0
|
|
-- olupas@opencores.org
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Description : Implements the receive unit of the miniUART core. Samples
|
-- Description : Implements the receive unit of the miniUART core. Samples
|
-- 16 times the RxD line and retain the value in the middle of
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-- 16 times the RxD line and retain the value in the middle of
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-- the time interval.
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-- the time interval.
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
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| Line 57... |
Line 58... |
architecture Behaviour of RxUnit is
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architecture Behaviour of RxUnit is
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Signals
|
-- Signals
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
signal Start : Std_Logic; -- Syncro signal
|
signal Start : Std_Logic; -- Syncro signal
|
signal tmpRxD : Std_Logic; --
|
signal tmpRxD : Std_Logic; -- RxD buffer
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signal tmpDRdy : Std_Logic; --
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signal tmpDRdy : Std_Logic; -- Data ready buffer
|
signal outErr : Std_Logic; --
|
signal outErr : Std_Logic; --
|
signal frameErr : Std_Logic; --
|
signal frameErr : Std_Logic; --
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signal BitCnt : Unsigned(3 downto 0); --
|
signal BitCnt : Unsigned(3 downto 0); --
|
signal SampleCnt : Unsigned(3 downto 0); --
|
signal SampleCnt : Unsigned(3 downto 0); -- samples on one bit counter
|
signal ShtReg : Std_Logic_Vector(7 downto 0); --
|
signal ShtReg : Std_Logic_Vector(7 downto 0); --
|
signal DOut : Std_Logic_Vector(7 downto 0); --
|
signal DOut : Std_Logic_Vector(7 downto 0); --
|
begin
|
begin
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
-- Receiver process
|
-- Receiver process
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| Line 82... |
Line 83... |
if Reset = '0' then
|
if Reset = '0' then
|
BitCnt <= "0000";
|
BitCnt <= "0000";
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SampleCnt <= "0000";
|
SampleCnt <= "0000";
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Start <= '0';
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Start <= '0';
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tmpDRdy <= '0';
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tmpDRdy <= '0';
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tmpRxD <= '1';
|
|
frameErr <= '0';
|
frameErr <= '0';
|
outErr <= '0';
|
outErr <= '0';
|
|
|
ShtReg <= "00000000"; --
|
ShtReg <= "00000000"; --
|
DOut <= "00000000"; --
|
DOut <= "00000000"; --
|
| Line 106... |
Line 106... |
tmpRxD <= RxD;
|
tmpRxD <= RxD;
|
SampleCnt <= SampleCnt + CntOne;
|
SampleCnt <= SampleCnt + CntOne;
|
elsif tmpSampleCnt = 15 then
|
elsif tmpSampleCnt = 15 then
|
case tmpBitCnt is
|
case tmpBitCnt is
|
when 0 =>
|
when 0 =>
|
if RxD = '1' then
|
if tmpRxD = '1' then -- Start Bit
|
Start <= '0';
|
Start <= '0';
|
else
|
else
|
BitCnt <= BitCnt + CntOne;
|
BitCnt <= BitCnt + CntOne;
|
end if;
|
end if;
|
|
SampleCnt <= SampleCnt + CntOne;
|
when 1|2|3|4|5|6|7|8 =>
|
when 1|2|3|4|5|6|7|8 =>
|
BitCnt <= BitCnt + CntOne;
|
BitCnt <= BitCnt + CntOne;
|
SampleCnt <= SampleCnt + CntOne;
|
SampleCnt <= SampleCnt + CntOne;
|
ShtReg <= tmpRxD & ShtReg(7 downto 1);
|
ShtReg <= tmpRxD & ShtReg(7 downto 1);
|
when 9 =>
|
when 9 =>
|
