| Line 22... |
Line 22... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Revision list
|
-- Revision list
|
-- Version Author Date Changes
|
-- Version Author Date Changes
|
--
|
--
|
-- 0.1 Ovidiu Lupas 15 January 2000 New model
|
-- 0.1 Ovidiu Lupas 15 January 2000 New model
|
-- ovilup@mail.dnttm.ro
|
-- 1.0 Ovidiu Lupas January 2000 Synthesis optimizations
|
|
-- 2.0 Ovidiu Lupas April 2000 Bugs removed - RSBusCtrl
|
|
-- the RSBusCtrl did not process all possible situations
|
|
--
|
|
-- olupas@opencores.org
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Description : The memory consists of a dual-port memory addressed by
|
-- Description : The memory consists of a dual-port memory addressed by
|
-- two counters (RdCnt & WrCnt). The third counter (StatCnt)
|
-- two counters (RdCnt & WrCnt). The third counter (StatCnt)
|
-- sets the status signals and keeps a track of the data flow.
|
-- sets the status signals and keeps a track of the data flow.
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
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| Line 125... |
Line 129... |
RxDev : RxUnit port map (SysClk,Reset,EnabRX,RxD,Read,FErr,OErr,DRdy,RxData);
|
RxDev : RxUnit port map (SysClk,Reset,EnabRX,RxD,Read,FErr,OErr,DRdy,RxData);
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Implements the controller for Rx&Tx units
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-- Implements the controller for Rx&Tx units
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
RSBusCtrl : process(SysClk,Reset,Read,Load)
|
RSBusCtrl : process(SysClk,Reset,Read,Load)
|
variable StatM : unsigned(4 downto 0);
|
variable StatM : Std_Logic_Vector(4 downto 0);
|
begin
|
begin
|
if Rising_Edge(SysClk) then
|
if Rising_Edge(SysClk) then
|
if Reset = '0' then
|
if Reset = '0' then
|
StatM := "00000";
|
StatM := "00000";
|
IntTx_N <= '1';
|
IntTx_N <= '1';
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| Line 144... |
Line 148... |
end if;
|
end if;
|
case StatM is
|
case StatM is
|
when "00001" =>
|
when "00001" =>
|
IntRx_N <= '0';
|
IntRx_N <= '0';
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CSReg(2) <= '1';
|
CSReg(2) <= '1';
|
|
when "10001" =>
|
|
IntRx_N <= '0';
|
|
CSReg(2) <= '1';
|
when "01000" =>
|
when "01000" =>
|
IntTx_N <= '0';
|
IntTx_N <= '0';
|
when "11000" =>
|
when "11000" =>
|
IntTx_N <= '0';
|
IntTx_N <= '0';
|
CSReg(3) <= '1';
|
CSReg(3) <= '1';
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| Line 193... |
Line 200... |
elsif (Load = '1' and Addr = "00") then
|
elsif (Load = '1' and Addr = "00") then
|
TxData <= DataIn;
|
TxData <= DataIn;
|
end if;
|
end if;
|
end process;
|
end process;
|
end uart; --===================== End of architecture =======================--
|
end uart; --===================== End of architecture =======================--
|
|
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No newline at end of file
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No newline at end of file
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