URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] [raminfr.v] - Diff between revs 79 and 84

Rev 79	Rev 84
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`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2002/07/22 23:02:23 gorban`
	`// Bug Fixes:`
	`// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.`
	`// Problem reported by Kenny.Tung.`
	`// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.`
	`//`
	`// Improvements:`
	`// * Made FIFO's as general inferrable memory where possible.`
	`// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).`
	`// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.`
	`//`
	`// * Added optional baudrate output (baud_o).`
	`// This is identical to BAUDOUT* signal on 16550 chip.`
	`// It outputs 16xbit_clock_rate - the divided clock.`
	`// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.`
	`//`

`//Following is the Verilog code for a dual-port RAM with asynchronous read.`	`//Following is the Verilog code for a dual-port RAM with asynchronous read.`
`module raminfr`	`module raminfr`
`(clk, we, a, dpra, di, dpo);`	`(clk, we, a, dpra, di, dpo);`