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Line 52... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/12/12 22:17:30 gorban
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// some synthesis bugs fixed
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//
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// Revision 1.1 2001/12/04 21:14:16 gorban
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// Revision 1.1 2001/12/04 21:14:16 gorban
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// committed the debug interface file
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// committed the debug interface file
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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Line 69... |
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module uart_debug_if (/*AUTOARG*/
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module uart_debug_if (/*AUTOARG*/
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// Outputs
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// Outputs
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wb_dat32_o,
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wb_dat32_o,
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// Inputs
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// Inputs
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wb_clk_i, wb_rst_i, wb_adr_i, re_o, ier, iir, fcr, mcr, lcr, msr,
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wb_adr_i, ier, iir, fcr, mcr, lcr, msr,
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lsr, rf_count, tf_count, tstate, rstate
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lsr, rf_count, tf_count, tstate, rstate
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) ;
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) ;
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input wb_clk_i;
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input wb_rst_i;
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input [`UART_ADDR_WIDTH-1:0] wb_adr_i;
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input [`UART_ADDR_WIDTH-1:0] wb_adr_i;
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output [31:0] wb_dat32_o;
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output [31:0] wb_dat32_o;
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input re_o;
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input [3:0] ier;
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input [3:0] ier;
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input [3:0] iir;
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input [3:0] iir;
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input [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
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input [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
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input [4:0] mcr;
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input [4:0] mcr;
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input [7:0] lcr;
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input [7:0] lcr;
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