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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2001/11/26 21:38:54 gorban
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// Lots of fixes:
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// Break condition wasn't handled correctly at all.
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// LSR bits could lose their values.
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// LSR value after reset was wrong.
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// Timing of THRE interrupt signal corrected.
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// LSR bit 0 timing corrected.
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//
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// Revision 1.7 2001/08/24 21:01:12 mohor
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// Revision 1.7 2001/08/24 21:01:12 mohor
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// Things connected to parity changed.
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// Things connected to parity changed.
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// Clock devider changed.
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// Clock devider changed.
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//
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//
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// Revision 1.6 2001/08/23 16:05:05 mohor
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// Revision 1.6 2001/08/23 16:05:05 mohor
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// Revision 1.0 2001-05-17 21:27:11+02 jacob
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// Revision 1.0 2001-05-17 21:27:11+02 jacob
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// Initial revision
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// Initial revision
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//
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//
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//
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//
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// remove comments to restore use to the old version with 8 data bit interface
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// in new mode (32bit bus), the wb_sel_i signal is used to pus data in correct place
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// also, in 8-bit version there'll be no debugging features included
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// `define DATA_BUS_WIDTH_8
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`ifdef DATA_BUS_WIDTH_8
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`define UART_ADDR_WIDTH 3
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`define UART_ADDR_WIDTH 3
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`define UART_DATA_WIDTH 8
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`else
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`define UART_ADDR_WIDTH 5
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`define UART_DATA_WIDTH 32
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`endif
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// Register addresses
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// Register addresses
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`define UART_REG_RB 3'd0 // receiver buffer
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`define UART_REG_RB `UART_ADDR_WIDTH'd0 // receiver buffer
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`define UART_REG_TR 3'd0 // transmitter
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`define UART_REG_TR `UART_ADDR_WIDTH'd0 // transmitter
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`define UART_REG_IE 3'd1 // Interrupt enable
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`define UART_REG_IE `UART_ADDR_WIDTH'd1 // Interrupt enable
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`define UART_REG_II 3'd2 // Interrupt identification
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`define UART_REG_II `UART_ADDR_WIDTH'd2 // Interrupt identification
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`define UART_REG_FC 3'd2 // FIFO control
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`define UART_REG_FC `UART_ADDR_WIDTH'd2 // FIFO control
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`define UART_REG_LC 3'd3 // Line Control
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`define UART_REG_LC `UART_ADDR_WIDTH'd3 // Line Control
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`define UART_REG_MC 3'd4 // Modem control
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`define UART_REG_MC `UART_ADDR_WIDTH'd4 // Modem control
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`define UART_REG_LS 3'd5 // Line status
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`define UART_REG_LS `UART_ADDR_WIDTH'd5 // Line status
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`define UART_REG_MS 3'd6 // Modem status
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`define UART_REG_MS `UART_ADDR_WIDTH'd6 // Modem status
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`define UART_REG_DL1 3'd0 // Divisor latch bytes (1-4)
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`define UART_REG_DL1 `UART_ADDR_WIDTH'd0 // Divisor latch bytes (1-2)
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`define UART_REG_DL2 3'd1
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`define UART_REG_DL2 `UART_ADDR_WIDTH'd1
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`define UART_REG_DL3 3'd4
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`define UART_REG_DL4 3'd5
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// Interrupt Enable register bits
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// Interrupt Enable register bits
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`define UART_IE_RDA 0 // Received Data available interrupt
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`define UART_IE_RDA 0 // Received Data available interrupt
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`define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt
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`define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt
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`define UART_IE_RLS 2 // Receiver Line Status Interrupt
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`define UART_IE_RLS 2 // Receiver Line Status Interrupt
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`define UART_MS_CCTS 4 // Complement signals
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`define UART_MS_CCTS 4 // Complement signals
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`define UART_MS_CDSR 5
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`define UART_MS_CDSR 5
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`define UART_MS_CRI 6
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`define UART_MS_CRI 6
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`define UART_MS_CDCD 7
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`define UART_MS_CDCD 7
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// FIFO parameter defines
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// FIFO parameter defines
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`define UART_FIFO_WIDTH 8
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`define UART_FIFO_WIDTH 8
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`define UART_FIFO_DEPTH 16
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`define UART_FIFO_DEPTH 16
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`define UART_FIFO_POINTER_W 4
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`define UART_FIFO_POINTER_W 4
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`define UART_FIFO_COUNTER_W 5
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`define UART_FIFO_COUNTER_W 5
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// receiver fifo has width 11 because it has break, parity and framing error bits
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// receiver fifo has width 11 because it has break, parity and framing error bits
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`define UART_FIFO_REC_WIDTH 11
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`define UART_FIFO_REC_WIDTH 11
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`define VERBOSE_WB 0 // All activity on the WISHBONE is recorded
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`define VERBOSE_LINE_STATUS 0 // Details about the lsr (line status register)
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`define FAST_TEST 1 // 64/1024 packets are sent
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`define VERBOSE_WB 0 // All activity on the WISHBONE is recorded
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`define VERBOSE_LINE_STATUS 0 // Details about the lsr (line status register)
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`define FAST_TEST 1 // 64/1024 packets are sent
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No newline at end of file
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No newline at end of file
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