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Line 61... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2001/12/11 08:55:40 mohor
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// Scratch register define added.
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//
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// Revision 1.9 2001/12/03 21:44:29 gorban
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// Revision 1.9 2001/12/03 21:44:29 gorban
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// Updated specification documentation.
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// Updated specification documentation.
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// Added full 32-bit data bus interface, now as default.
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// Added full 32-bit data bus interface, now as default.
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// Address is 5-bit wide in 32-bit data bus mode.
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// Address is 5-bit wide in 32-bit data bus mode.
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// Added wb_sel_i input to the core. It's used in the 32-bit mode.
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// Added wb_sel_i input to the core. It's used in the 32-bit mode.
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// remove comments to restore use to the old version with 8 data bit interface
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// remove comments to restore use to the old version with 8 data bit interface
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// in new mode (32bit bus), the wb_sel_i signal is used to pus data in correct place
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// in new mode (32bit bus), the wb_sel_i signal is used to pus data in correct place
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// also, in 8-bit version there'll be no debugging features included
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// also, in 8-bit version there'll be no debugging features included
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// `define DATA_BUS_WIDTH_8
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// `define DATA_BUS_WIDTH_8
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`define BIG_BYTE_ENDIAN // Defines endian
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`ifdef DATA_BUS_WIDTH_8
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`ifdef DATA_BUS_WIDTH_8
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`define UART_ADDR_WIDTH 3
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`define UART_ADDR_WIDTH 3
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`define UART_DATA_WIDTH 8
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`define UART_DATA_WIDTH 8
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`else
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`else
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`define UART_ADDR_WIDTH 5
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`define UART_ADDR_WIDTH 5
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