URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_receiver.v] - Diff between revs 39 and 40

Rev 39	Rev 40
Line 61...	Line 61...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.13 2001/11/08 14:54:23 mohor`
	`// Comments in Slovene language deleted, few small fixes for better work of`
	`// old tools. IRQs need to be fix.`
	`//`
`// Revision 1.12 2001/11/07 17:51:52 gorban`	`// Revision 1.12 2001/11/07 17:51:52 gorban`
`// Heavily rewritten interrupt and LSR subsystems.`	`// Heavily rewritten interrupt and LSR subsystems.`
`// Many bugs hopefully squashed.`	`// Many bugs hopefully squashed.`
`//`	`//`
`// Revision 1.11 2001/10/31 15:19:22 gorban`	`// Revision 1.11 2001/10/31 15:19:22 gorban`
Line 324...	Line 328...
`end // always of receiver`	`end // always of receiver`

`//`	`//`
`// Break condition detection.`	`// Break condition detection.`
`// Works in conjuction with the receiver state machine`	`// Works in conjuction with the receiver state machine`
`reg [7:0] counter_b; // counts the 1 (idle) signals`	`reg [7:0] counter_b; // counts the 0 (low) signals`

`always @(posedge clk or posedge wb_rst_i)`	`always @(posedge clk or posedge wb_rst_i)`
`begin`	`begin`
`if (wb_rst_i)`	`if (wb_rst_i)`
`counter_b <= #1 8'd191;`	`counter_b <= #1 8'd191;`