URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_receiver.v] - Diff between revs 66 and 67

Rev 66	Rev 67
Line 61...	Line 61...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.25 2001/12/20 13:25:46 mohor`
	`// rx push changed to be only one cycle wide.`
	`//`
`// Revision 1.24 2001/12/19 08:03:34 mohor`	`// Revision 1.24 2001/12/19 08:03:34 mohor`
`// Warnings cleared.`	`// Warnings cleared.`
`//`	`//`
`// Revision 1.23 2001/12/19 07:33:54 mohor`	`// Revision 1.23 2001/12/19 07:33:54 mohor`
`// Synplicity was having troubles with the comment.`	`// Synplicity was having troubles with the comment.`
Line 194...	Line 197...
`reg rparity_error;`	`reg rparity_error;`
`reg rframing_error; // framing error flag`	`reg rframing_error; // framing error flag`
`reg rbit_in;`	`reg rbit_in;`
`reg rparity_xor;`	`reg rparity_xor;`
`reg [7:0] counter_b; // counts the 0 (low) signals`	`reg [7:0] counter_b; // counts the 0 (low) signals`
	`reg rf_push_q;`

`// RX FIFO signals`	`// RX FIFO signals`
reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in;	reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in;
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;	wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
`wire rf_push_pulse;`	`wire rf_push_pulse;`