| Line 61... |
Line 61... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.26 2001/12/20 13:28:27 mohor
|
|
// Missing declaration of rf_push_q fixed.
|
|
//
|
// Revision 1.25 2001/12/20 13:25:46 mohor
|
// Revision 1.25 2001/12/20 13:25:46 mohor
|
// rx push changed to be only one cycle wide.
|
// rx push changed to be only one cycle wide.
|
//
|
//
|
// Revision 1.24 2001/12/19 08:03:34 mohor
|
// Revision 1.24 2001/12/19 08:03:34 mohor
|
// Warnings cleared.
|
// Warnings cleared.
|
| Line 262... |
Line 265... |
rshift <= #1 0;
|
rshift <= #1 0;
|
rf_push <= #1 1'b0;
|
rf_push <= #1 1'b0;
|
rf_data_in <= #1 0;
|
rf_data_in <= #1 0;
|
end
|
end
|
else
|
else
|
// if (break_error && rstate != sr_idle) // break condition met while receiver is not idle
|
|
// begin
|
|
// rstate <= #1 sr_idle;
|
|
// rf_data_in <= #1 {8'b0, 3'b100}; // break input (empty character) to receiver FIFO
|
|
// rf_push <= #1 1'b1;
|
|
// end
|
|
// else
|
|
if (enable)
|
if (enable)
|
begin
|
begin
|
case (rstate)
|
case (rstate)
|
sr_idle : begin
|
sr_idle : begin
|
rf_push <= #1 1'b0;
|
rf_push <= #1 1'b0;
|
rf_data_in <= #1 0;
|
rf_data_in <= #1 0;
|
if (srx_pad_i==1'b0) // detected a pulse (start bit?)
|
if (srx_pad_i==1'b0 & ~break_error) // detected a pulse (start bit?)
|
begin
|
begin
|
rstate <= #1 sr_rec_start;
|
rstate <= #1 sr_rec_start;
|
rcounter16 <= #1 4'b1110;
|
rcounter16 <= #1 4'b1110;
|
end
|
end
|
end
|
end
|
| Line 387... |
Line 383... |
rstate <= #1 sr_last;
|
rstate <= #1 sr_last;
|
end
|
end
|
|
|
end
|
end
|
sr_last : begin
|
sr_last : begin
|
// if (rcounter16_eq_1)
|
if (rcounter16_eq_1 & srx_pad_i | break_error)
|
if (rcounter16_eq_1 & srx_pad_i) // igor
|
|
rstate <= #1 sr_idle;
|
rstate <= #1 sr_idle;
|
rcounter16 <= #1 rcounter16_minus_1;
|
rcounter16 <= #1 rcounter16_minus_1;
|
rf_push <= #1 1'b0;
|
rf_push <= #1 1'b0;
|
end
|
end
|
default : rstate <= #1 sr_idle;
|
default : rstate <= #1 sr_idle;
|
| Line 435... |
Line 430... |
always @(posedge clk or posedge wb_rst_i)
|
always @(posedge clk or posedge wb_rst_i)
|
begin
|
begin
|
if (wb_rst_i)
|
if (wb_rst_i)
|
counter_b <= #1 8'd159;
|
counter_b <= #1 8'd159;
|
else
|
else
|
// if(lsr_mask) igor
|
|
// counter_b <= #1 brc_value;
|
|
// else
|
|
if (enable) // only work on enable times
|
|
if (srx_pad_i)
|
if (srx_pad_i)
|
counter_b <= #1 brc_value; // character time length - 1
|
counter_b <= #1 brc_value; // character time length - 1
|
else
|
else
|
if (counter_b != 8'b0) // break not reached it
|
if(enable & counter_b != 8'b0) // only work on enable times break not reached.
|
counter_b <= #1 counter_b - 1; // decrement break counter
|
counter_b <= #1 counter_b - 1; // decrement break counter
|
end // always of break condition detection
|
end // always of break condition detection
|
|
|
///
|
///
|
/// Timeout condition detection
|
/// Timeout condition detection
|
