URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_regs.v] - Diff between revs 45 and 47

Rev 45	Rev 47
Line 60...	Line 60...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.24 2001/11/26 21:38:54 gorban`
	`// Lots of fixes:`
	`// Break condition wasn't handled correctly at all.`
	`// LSR bits could lose their values.`
	`// LSR value after reset was wrong.`
	`// Timing of THRE interrupt signal corrected.`
	`// LSR bit 0 timing corrected.`
	`//`
`// Revision 1.23 2001/11/12 21:57:29 gorban`	`// Revision 1.23 2001/11/12 21:57:29 gorban`
`// fixed more typo bugs`	`// fixed more typo bugs`
`//`	`//`
`// Revision 1.22 2001/11/12 15:02:28 mohor`	`// Revision 1.22 2001/11/12 15:02:28 mohor`
`// lsr1r error fixed.`	`// lsr1r error fixed.`
Line 324...	Line 332...
`msi_reset <= #1 0;`	`msi_reset <= #1 0;`
`else`	`else`
`if (msi_reset)`	`if (msi_reset)`
`msi_reset <= #1 0;`	`msi_reset <= #1 0;`
`else`	`else`
if (wb_re_i && wb_addr_i == `UART_REG_MS)	`if (msr_read)`
`msi_reset <= #1 1; // reset bits in Modem Status Register`	`msi_reset <= #1 1; // reset bits in Modem Status Register`
`end`	`end`

`/*`	`/*`
`// threi_clear signal handling`	`// threi_clear signal handling`