| Line 60... |
Line 60... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.27 2001/12/06 14:51:04 gorban
|
|
// Bug in LSR[0] is fixed.
|
|
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
|
|
//
|
// Revision 1.26 2001/12/03 21:44:29 gorban
|
// Revision 1.26 2001/12/03 21:44:29 gorban
|
// Updated specification documentation.
|
// Updated specification documentation.
|
// Added full 32-bit data bus interface, now as default.
|
// Added full 32-bit data bus interface, now as default.
|
// Address is 5-bit wide in 32-bit data bus mode.
|
// Address is 5-bit wide in 32-bit data bus mode.
|
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
|
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
|
| Line 231... |
Line 235... |
reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
|
reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
|
reg [4:0] mcr;
|
reg [4:0] mcr;
|
reg [7:0] lcr;
|
reg [7:0] lcr;
|
reg [7:0] msr;
|
reg [7:0] msr;
|
reg [15:0] dl; // 32-bit divisor latch
|
reg [15:0] dl; // 32-bit divisor latch
|
|
reg [7:0] scratch; // UART scratch register
|
reg start_dlc; // activate dlc on writing to UART_DL1
|
reg start_dlc; // activate dlc on writing to UART_DL1
|
reg lsr_mask_d; // delay for lsr_mask condition
|
reg lsr_mask_d; // delay for lsr_mask condition
|
reg msi_reset; // reset MSR 4 lower bits indicator
|
reg msi_reset; // reset MSR 4 lower bits indicator
|
//reg threi_clear; // THRE interrupt clear flag
|
//reg threi_clear; // THRE interrupt clear flag
|
reg [15:0] dlc; // 32-bit divisor latch counter
|
reg [15:0] dlc; // 32-bit divisor latch counter
|
| Line 299... |
Line 304... |
uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, rda_int,
|
uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, rda_int,
|
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push);
|
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push);
|
|
|
|
|
// Asynchronous reading here because the outputs are sampled in uart_wb.v file
|
// Asynchronous reading here because the outputs are sampled in uart_wb.v file
|
always @(/*AUTOSENSE*/dl or dlab or ier or iir
|
always @(dl or dlab or ier or iir or scratch
|
or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading
|
or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading
|
begin
|
begin
|
if (wb_rst_i)
|
|
begin
|
|
wb_dat_o <= #1 8'b0;
|
|
end
|
|
else
|
|
if (wb_re_i) //if (we're not writing)
|
|
case (wb_addr_i)
|
case (wb_addr_i)
|
`UART_REG_RB : wb_dat_o <= #1 dlab ? dl[`UART_DL1] : rf_data_out[10:3];
|
`UART_REG_RB : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];
|
`UART_REG_IE : wb_dat_o <= #1 dlab ? dl[`UART_DL2] : ier;
|
`UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : ier;
|
`UART_REG_II : wb_dat_o <= #1 {4'b1100,iir};
|
`UART_REG_II : wb_dat_o = {4'b1100,iir};
|
`UART_REG_LC : wb_dat_o <= #1 lcr;
|
`UART_REG_LC : wb_dat_o = lcr;
|
`UART_REG_LS : wb_dat_o <= #1 lsr;
|
`UART_REG_LS : wb_dat_o = lsr;
|
`UART_REG_MS : wb_dat_o <= #1 msr;
|
`UART_REG_MS : wb_dat_o = msr;
|
default: wb_dat_o <= #1 8'b0; // ??
|
`UART_REG_SR : wb_dat_o = scratch;
|
|
default: wb_dat_o = 8'b0; // ??
|
endcase // case(wb_addr_i)
|
endcase // case(wb_addr_i)
|
else
|
end // always @ (dl or dlab or ier or iir or scratch...
|
wb_dat_o <= #1 8'b0;
|
|
end // always @ (posedge clk or posedge wb_rst_i)
|
|
|
|
// rf_pop signal handling
|
// rf_pop signal handling
|
always @(posedge clk or posedge wb_rst_i)
|
always @(posedge clk or posedge wb_rst_i)
|
begin
|
begin
|
if (wb_rst_i)
|
if (wb_rst_i)
|
| Line 424... |
Line 423... |
mcr <= #1 5'b0;
|
mcr <= #1 5'b0;
|
else
|
else
|
if (wb_we_i && wb_addr_i==`UART_REG_MC)
|
if (wb_we_i && wb_addr_i==`UART_REG_MC)
|
mcr <= #1 wb_dat_i[4:0];
|
mcr <= #1 wb_dat_i[4:0];
|
|
|
|
// Scratch register
|
|
// Line Control Register
|
|
always @(posedge clk or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
scratch <= #1 0; // 8n1 setting
|
|
else
|
|
if (wb_we_i && wb_addr_i==`UART_REG_SR)
|
|
scratch <= #1 wb_dat_i;
|
|
|
// TX_FIFO or UART_DL1
|
// TX_FIFO or UART_DL1
|
always @(posedge clk or posedge wb_rst_i)
|
always @(posedge clk or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
begin
|
begin
|
dl[`UART_DL1] <= #1 8'b0;
|
dl[`UART_DL1] <= #1 8'b0;
|
