| Line 60... |
Line 60... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.30 2001/12/13 10:09:13 mohor
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// thre irq should be cleared only when being source of interrupt.
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//
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// Revision 1.29 2001/12/12 09:05:46 mohor
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// Revision 1.29 2001/12/12 09:05:46 mohor
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// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).
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// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).
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//
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//
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// Revision 1.28 2001/12/10 19:52:41 gorban
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// Revision 1.28 2001/12/10 19:52:41 gorban
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// Scratch register added
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// Scratch register added
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| Line 367... |
Line 370... |
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// msi_reset signal handling
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// msi_reset signal handling
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always @(posedge clk or posedge wb_rst_i)
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always @(posedge clk or posedge wb_rst_i)
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begin
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begin
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if (wb_rst_i)
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if (wb_rst_i)
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msi_reset <= #1 0;
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msi_reset <= #1 1;
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else
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else
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if (msi_reset)
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if (msi_reset)
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msi_reset <= #1 0;
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msi_reset <= #1 0;
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else
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else
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if (msr_read)
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if (msr_read)
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| Line 490... |
Line 493... |
msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ msr[`UART_MS_CDCD:`UART_MS_CCTS]);
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msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ msr[`UART_MS_CDCD:`UART_MS_CCTS]);
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msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd, ri, dsr, cts};
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msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd, ri, dsr, cts};
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end
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end
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end
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end
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// Line Status Register
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// Line Status Register
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// activation conditions
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// activation conditions
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assign lsr0 = (rf_count==0 && rf_push); // data in receiver fifo available set condition
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assign lsr0 = (rf_count==0 && rf_push); // data in receiver fifo available set condition
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assign lsr1 = rf_overrun; // Receiver overrun error
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assign lsr1 = rf_overrun; // Receiver overrun error
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