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Line 60... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.31 2001/12/14 10:06:58 mohor
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// After reset modem status register MSR should be reset.
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//
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// Revision 1.30 2001/12/13 10:09:13 mohor
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// Revision 1.30 2001/12/13 10:09:13 mohor
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// thre irq should be cleared only when being source of interrupt.
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// thre irq should be cleared only when being source of interrupt.
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//
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//
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// Revision 1.29 2001/12/12 09:05:46 mohor
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// Revision 1.29 2001/12/12 09:05:46 mohor
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// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).
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// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).
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Line 263... |
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wire dlab; // divisor latch access bit
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wire dlab; // divisor latch access bit
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wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits
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wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits
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wire loopback; // loopback bit (MCR bit 4)
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wire loopback; // loopback bit (MCR bit 4)
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wire cts, dsr, ri, dcd; // effective signals (considering loopback)
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wire cts, dsr, ri, dcd; // effective signals (considering loopback)
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wire cts_c, dsr_c, ri_c, dcd_c; // Complement effective signals (considering loopback)
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wire rts_pad_o, dtr_pad_o; // modem control outputs
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wire rts_pad_o, dtr_pad_o; // modem control outputs
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// LSR bits wires and regs
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// LSR bits wires and regs
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wire [7:0] lsr;
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wire [7:0] lsr;
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wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7;
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wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7;
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Line 279... |
//
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//
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assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r };
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assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r };
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assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
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assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
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assign {cts, dsr, ri, dcd} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
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assign {cts, dsr, ri, dcd} = loopback ? {mcr[`UART_MC_DTR],mcr[`UART_MC_RTS],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
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: ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
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: ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
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assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
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: {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
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assign dlab = lcr[`UART_LC_DL];
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assign dlab = lcr[`UART_LC_DL];
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assign loopback = mcr[4];
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assign loopback = mcr[4];
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// assign modem outputs
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// assign modem outputs
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assign rts_pad_o = mcr[`UART_MC_RTS];
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assign rts_pad_o = mcr[`UART_MC_RTS];
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Line 489... |
//
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//
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// STATUS REGISTERS //
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// STATUS REGISTERS //
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//
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//
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// Modem Status Register
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// Modem Status Register
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reg [3:0] delayed_modem_signals;
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always @(posedge clk or posedge wb_rst_i)
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always @(posedge clk or posedge wb_rst_i)
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begin
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begin
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if (wb_rst_i)
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if (wb_rst_i)
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msr <= #1 0;
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msr <= #1 0;
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else begin
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else begin
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msr[`UART_MS_DDCD:`UART_MS_DCTS] <= #1 msi_reset ? 4'b0 :
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msr[`UART_MS_DDCD:`UART_MS_DCTS] <= #1 msi_reset ? 4'b0 :
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msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ msr[`UART_MS_CDCD:`UART_MS_CCTS]);
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msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]);
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msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd, ri, dsr, cts};
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msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd_c, ri_c, dsr_c, cts_c};
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delayed_modem_signals[3:0] <= #1 {dcd, ri, dsr, cts};
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end
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end
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end
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end
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