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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_regs.v] - Diff between revs 60 and 63

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Rev 60 Rev 63
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.33  2001/12/17 10:14:43  mohor
 
// Things related to msr register changed. After THRE IRQ occurs, and one
 
// character is written to the transmit fifo, the detection of the THRE bit in the
 
// LSR is delayed for one character time.
 
//
// Revision 1.32  2001/12/14 13:19:24  mohor
// Revision 1.32  2001/12/14 13:19:24  mohor
// MSR register fixed.
// MSR register fixed.
//
//
// Revision 1.31  2001/12/14 10:06:58  mohor
// Revision 1.31  2001/12/14 10:06:58  mohor
// After reset modem status register MSR should be reset.
// After reset modem status register MSR should be reset.
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//
//
// Revision 1.20  2001/11/12 14:50:27  mohor
// Revision 1.20  2001/11/12 14:50:27  mohor
// ti_int_d error fixed.
// ti_int_d error fixed.
//
//
// Revision 1.19  2001/11/10 12:43:21  gorban
// Revision 1.19  2001/11/10 12:43:21  gorban
// Synthesis bugs fixed. Some other minor changes
// Logic Synthesis bugs fixed. Some other minor changes
//
//
// Revision 1.18  2001/11/08 14:54:23  mohor
// Revision 1.18  2001/11/08 14:54:23  mohor
// Comments in Slovene language deleted, few small fixes for better work of
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
// old tools. IRQs need to be fix.
//
//

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