| Line 60... |
Line 60... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.34 2001/12/19 07:33:54 mohor
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// Synplicity was having troubles with the comment.
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//
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// Revision 1.33 2001/12/17 10:14:43 mohor
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// Revision 1.33 2001/12/17 10:14:43 mohor
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// Things related to msr register changed. After THRE IRQ occurs, and one
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// Things related to msr register changed. After THRE IRQ occurs, and one
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// character is written to the transmit fifo, the detection of the THRE bit in the
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// character is written to the transmit fifo, the detection of the THRE bit in the
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// LSR is delayed for one character time.
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// LSR is delayed for one character time.
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//
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//
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Line 328... |
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// Transmitter Instance
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// Transmitter Instance
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uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
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uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
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// Receiver Instance
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// Receiver Instance
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uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, rda_int,
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uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
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counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push);
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counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push);
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// Asynchronous reading here because the outputs are sampled in uart_wb.v file
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// Asynchronous reading here because the outputs are sampled in uart_wb.v file
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always @(dl or dlab or ier or iir or scratch
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always @(dl or dlab or ier or iir or scratch
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| Line 503... |
Line 506... |
// Modem Status Register
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// Modem Status Register
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reg [3:0] delayed_modem_signals;
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reg [3:0] delayed_modem_signals;
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always @(posedge clk or posedge wb_rst_i)
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always @(posedge clk or posedge wb_rst_i)
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begin
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begin
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if (wb_rst_i)
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if (wb_rst_i)
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begin
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msr <= #1 0;
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msr <= #1 0;
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delayed_modem_signals[3:0] <= #1 0;
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end
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else begin
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else begin
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msr[`UART_MS_DDCD:`UART_MS_DCTS] <= #1 msi_reset ? 4'b0 :
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msr[`UART_MS_DDCD:`UART_MS_DCTS] <= #1 msi_reset ? 4'b0 :
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msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]);
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msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]);
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msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd_c, ri_c, dsr_c, cts_c};
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msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd_c, ri_c, dsr_c, cts_c};
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delayed_modem_signals[3:0] <= #1 {dcd, ri, dsr, cts};
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delayed_modem_signals[3:0] <= #1 {dcd, ri, dsr, cts};
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