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Line 60... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.35 2001/12/19 08:03:34 mohor
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// Warnings cleared.
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//
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// Revision 1.34 2001/12/19 07:33:54 mohor
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// Revision 1.34 2001/12/19 07:33:54 mohor
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// Synplicity was having troubles with the comment.
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// Synplicity was having troubles with the comment.
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//
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//
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// Revision 1.33 2001/12/17 10:14:43 mohor
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// Revision 1.33 2001/12/17 10:14:43 mohor
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// Things related to msr register changed. After THRE IRQ occurs, and one
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// Things related to msr register changed. After THRE IRQ occurs, and one
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Line 332... |
// Transmitter Instance
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// Transmitter Instance
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uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
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uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
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// Receiver Instance
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// Receiver Instance
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uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
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uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
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counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push);
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counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
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// Asynchronous reading here because the outputs are sampled in uart_wb.v file
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// Asynchronous reading here because the outputs are sampled in uart_wb.v file
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always @(dl or dlab or ier or iir or scratch
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always @(dl or dlab or ier or iir or scratch
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or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading
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or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading
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Line 525... |
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// Line Status Register
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// Line Status Register
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// activation conditions
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// activation conditions
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assign lsr0 = (rf_count==0 && rf_push); // data in receiver fifo available set condition
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assign lsr0 = (rf_count==0 && rf_push_pulse); // data in receiver fifo available set condition
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assign lsr1 = rf_overrun; // Receiver overrun error
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assign lsr1 = rf_overrun; // Receiver overrun error
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assign lsr2 = rf_data_out[1]; // parity error bit
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assign lsr2 = rf_data_out[1]; // parity error bit
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assign lsr3 = rf_data_out[0]; // framing error bit
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assign lsr3 = rf_data_out[0]; // framing error bit
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assign lsr4 = rf_data_out[2]; // break error in the character
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assign lsr4 = rf_data_out[2]; // break error in the character
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assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty
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assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty
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