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https://opencores.org/ocsvn/uart16550/uart16550/trunk
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.36 2001/12/20 13:25:46 mohor
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// rx push changed to be only one cycle wide.
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//
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// Revision 1.35 2001/12/19 08:03:34 mohor
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// Revision 1.35 2001/12/19 08:03:34 mohor
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// Warnings cleared.
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// Warnings cleared.
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//
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//
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// Revision 1.34 2001/12/19 07:33:54 mohor
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// Revision 1.34 2001/12/19 07:33:54 mohor
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// Synplicity was having troubles with the comment.
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// Synplicity was having troubles with the comment.
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assign lsr2 = rf_data_out[1]; // parity error bit
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assign lsr2 = rf_data_out[1]; // parity error bit
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assign lsr3 = rf_data_out[0]; // framing error bit
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assign lsr3 = rf_data_out[0]; // framing error bit
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assign lsr4 = rf_data_out[2]; // break error in the character
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assign lsr4 = rf_data_out[2]; // break error in the character
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assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty
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assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty
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assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter empty
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assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter empty
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assign lsr7 = rf_error_bit;
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assign lsr7 = rf_error_bit | rf_overrun;
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// lsr bit0 (receiver data available)
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// lsr bit0 (receiver data available)
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reg lsr0_d;
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reg lsr0_d;
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always @(posedge clk or posedge wb_rst_i)
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always @(posedge clk or posedge wb_rst_i)
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